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route spare col

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Jesse Cirimelli-Low
2021-10-05 15:28:20 -07:00
parent 911f479ecb
commit 5792256db1
1 changed files with 1 additions and 1 deletions
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compiler/modules/port_data.py
+1 -1
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@@ -616,7 +616,7 @@ class port_data(design.design):
self.connect_bitlines(inst1=inst1,
inst1_bls_template=inst1_bls_templ,
inst2=inst2,
num_bits=self.word_size,
num_bits=self.word_size + self.num_spare_cols,
inst1_start_bit=start_bit)
def route_write_driver_to_column_mux_or_precharge_array(self, port):