From 5792256db15554c35ff42ae74da901a1ff85b22e Mon Sep 17 00:00:00 2001
From: Jesse Cirimelli-Low <jcirimel@ucsc.edu>
Date: Tue, 5 Oct 2021 15:28:20 -0700
Subject: [PATCH] route spare col

---
 compiler/modules/port_data.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/compiler/modules/port_data.py b/compiler/modules/port_data.py
index 7b329702..01ddad8a 100644
--- a/compiler/modules/port_data.py
+++ b/compiler/modules/port_data.py
@@ -616,7 +616,7 @@ class port_data(design.design):
             self.connect_bitlines(inst1=inst1,
                                   inst1_bls_template=inst1_bls_templ,
                                   inst2=inst2,
-                                  num_bits=self.word_size,
+                                  num_bits=self.word_size + self.num_spare_cols,
                                   inst1_start_bit=start_bit)
 
     def route_write_driver_to_column_mux_or_precharge_array(self, port):