diff --git a/compiler/characterizer/stimuli.py b/compiler/characterizer/stimuli.py
index c8ee0492..fb2e261d 100644
--- a/compiler/characterizer/stimuli.py
+++ b/compiler/characterizer/stimuli.py
@@ -58,14 +58,20 @@ class stimuli():
         for pin in pins:
             self.sf.write("{0} ".format(pin))
         for bank in range(OPTS.num_banks):
-            for row in range(int(OPTS.num_words / OPTS.words_per_row)):
-                for col in range(int(OPTS.word_size * OPTS.words_per_row)):
-                    self.sf.write("bitcell_Q_b{0}_r{1}_c{2} ".format(bank,row,col))
-                    self.sf.write("bitcell_Q_bar_b{0}_r{1}_c{2} ".format(bank,row,col))
+            row = int(OPTS.num_words / OPTS.words_per_row) - 1
+            col = int(OPTS.word_size * OPTS.words_per_row) - 1 
+            self.sf.write("bitcell_Q_b{0}_r{1}_c{2} ".format(bank,row,col))
+            self.sf.write("bitcell_Q_bar_b{0}_r{1}_c{2} ".format(bank,row,col))
+        #    can't add all bitcells to top level due to ngspice max port count of 1005
+        #    for row in range(int(OPTS.num_words / OPTS.words_per_row)):
+        #        for col in range(int(OPTS.word_size * OPTS.words_per_row)):
+        #            self.sf.write("bitcell_Q_b{0}_r{1}_c{2} ".format(bank,row,col))
+        #            self.sf.write("bitcell_Q_bar_b{0}_r{1}_c{2} ".format(bank,row,col))
+        for bank in range(OPTS.num_banks):
             for col in range(OPTS.word_size * OPTS.words_per_row):
                 for port in range(OPTS.num_r_ports + OPTS.num_w_ports + OPTS.num_rw_ports):
-                    self.sf.write("bl{0}_{2} ".format(port, row, col))
-                    self.sf.write("br{0}_{2} ".format(port, row, col))
+                    self.sf.write("bl{0}_{1} ".format(port, col))
+                    self.sf.write("br{0}_{1} ".format(port, col))
                   
 
             self.sf.write("s_en{0} ".format(bank))
diff --git a/compiler/verify/magic.py b/compiler/verify/magic.py
index de206b87..c2960aa6 100644
--- a/compiler/verify/magic.py
+++ b/compiler/verify/magic.py
@@ -415,14 +415,15 @@ def correct_port(name, output_file_name, ref_file_name):
 
     bitcell_list = "+ "
     for bank in range(OPTS.num_banks):
-        for row in range(int(OPTS.num_words / OPTS.words_per_row)):
-            for col in range(int(OPTS.word_size * OPTS.words_per_row)):
-                bitcell_list += "bitcell_Q_b{0}_r{1}_c{2} ".format(bank, row, col)
-                bitcell_list += "bitcell_Q_bar_b{0}_r{1}_c{2} ".format(bank, row, col)
+        for bank in range(OPTS.num_banks):
+            row = int(OPTS.num_words / OPTS.words_per_row) - 1
+            col = int(OPTS.word_size * OPTS.words_per_row) - 1 
+            bitcell_list += "bitcell_Q_b{0}_r{1}_c{2} ".format(bank,row,col)
+            bitcell_list += "bitcell_Q_bar_b{0}_r{1}_c{2} ".format(bank,row,col)
         for col in range(OPTS.word_size * OPTS.words_per_row):
             for port in range(OPTS.num_r_ports + OPTS.num_w_ports + OPTS.num_rw_ports):
-                bitcell_list += "bl{0}_{2} ".format(bank, row, col)
-                bitcell_list += "br{0}_{2} ".format(bank, row, col)
+                bitcell_list += "bl{0}_{1} ".format(bank, col)
+                bitcell_list += "br{0}_{1} ".format(bank, col)
     bitcell_list += "\n"
 
     control_list = "+ "