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Change rom_base_bank name and top pin names
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@@ -72,7 +72,7 @@ from .replica_pbitcell import *
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from .row_cap_array import *
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from .row_cap_bitcell_1port import *
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from .row_cap_bitcell_2port import *
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from .rom_base_bank import *
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from .rom_bank import *
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from .sense_amp_array import *
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from .sense_amp import *
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from .tri_gate_array import *
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