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Add sram_config class. Rename port variables for better description.

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This commit is contained in:
Matt Guthaus
2018-08-31 12:03:28 -07:00
parent 77277e19a6
commit 563ff77d44
26 changed files with 548 additions and 411 deletions
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compiler/tests/08_precharge_array_test.py
+3 -3
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@@ -24,9 +24,9 @@ class precharge_test(openram_test):
debug.info(2, "Checking precharge for pbitcell")
OPTS.bitcell = "pbitcell"
OPTS.rw_ports = 2
OPTS.r_ports = 2
OPTS.w_ports = 2
OPTS.num_rw_ports = 2
OPTS.num_r_ports = 2
OPTS.num_w_ports = 2
pc = precharge_array.precharge_array(columns=3, bitcell_bl="rwbl0", bitcell_br="rwbl_bar0")
self.local_check(pc)