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Merge branch 'multiport' of https://github.com/VLSIDA/PrivateRAM into multiport

This commit is contained in:
Michael Timothy Grimes 2018-08-29 16:17:59 -07:00
parent e118cc2d5c e36452622c
commit 77277e19a6
2 changed files with 4 additions and 4 deletions
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4
technology/freepdk45/tech/tech.py
View File

@ -98,6 +98,8 @@ drc["minwidth_poly"] = 0.05
drc["poly_to_poly"] = 0.14
# POLY.3 Minimum poly extension beyond active
drc["poly_extend_active"] = 0.055
# Not a rule
drc["poly_to_polycontact"] = 0.075
# POLY.4 Minimum enclosure of active around gate
drc["active_enclosure_gate"] = 0.07
# POLY.5 Minimum spacing of field poly to active
@ -106,8 +108,6 @@ drc["poly_to_active"] = 0.05
drc["poly_to_field_poly"] = 0.075
# Not a rule
drc["minarea_poly"] = 0.0
# Not a rule
drc["poly_to_polycontact"] = 0.075
# ACTIVE.2 Minimum spacing of active
drc["active_to_body_active"] = 0.08

4
technology/scn3me_subm/tech/tech.py
View File

@ -87,10 +87,10 @@ drc["poly_extend_active"] = 0.6
drc["poly_to_polycontact"] = 1.2
# ??
drc["active_enclosure_gate"] = 0.0
# 3.2.a Minimum spacing over field poly
drc["poly_to_field_poly"] = 0.9
# 3.5 Minimum field poly to active
drc["poly_to_active"] = 0.3
# 3.2.a Minimum spacing over field poly
drc["poly_to_field_poly"] = 0.9
# Not a rule
drc["minarea_poly"] = 0.0