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single port bitcell array done

This commit is contained in:
jcirimel 2020-09-16 05:46:14 -07:00
parent d22164bd48
commit 559dfbc7a6
2 changed files with 45 additions and 32 deletions
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47
compiler/modules/bitcell_array.py
View File

@ -73,12 +73,47 @@ class bitcell_array(bitcell_base_array):
def create_instances(self): def create_instances(self):
""" Create the module instances used in this design """ """ Create the module instances used in this design """
self.cell_inst = {} self.cell_inst = {}
for col in range(self.column_size): if OPTS.tech_name != "sky130":
for row in range(self.row_size): for col in range(self.column_size):
name = "bit_r{0}_c{1}".format(row, col) for row in range(self.row_size):
self.cell_inst[row, col]=self.add_inst(name=name, name = "bit_r{0}_c{1}".format(row, col)
mod=self.cell) self.cell_inst[row, col]=self.add_inst(name=name,
self.connect_inst(self.get_bitcell_pins(row, col)) mod=self.cell)
self.connect_inst(self.get_bitcell_pins(row, col))
else:
self.array_layout = []
for row in range(0,self.row_size):
row_layout = []
alternate_bitcell = 1
alternate_strap = 1
for col in range(0,self.column_size):
if alternate_bitcell == 1:
row_layout.append(self.cell)
self.cell_inst[row, col]=self.add_inst(name="row_{}, col_{}_bitcell".format(row,col),
mod=self.cell)
alternate_bitcell = 0
else:
row_layout.append(self.cell2)
self.cell_inst[row, col]=self.add_inst(name="row_{}, col_{}_bitcell".format(row,col),
mod=self.cell2)
alternate_bitcell = 1
self.connect_inst(self.get_bitcell_pins(row, col))
if col != self.column_size-1:
if alternate_strap:
row_layout.append(self.strap2)
self.add_inst(name="row_{}, col_{}_wlstrap".format(row,col),
mod=self.strap2)
alternate_strap = 0
else:
row_layout.append(self.strap)
self.add_inst(name="row_{}, col_{}_wlstrap".format(row,col),
mod=self.strap)
alternate_strap = 1
self.connect_inst([])
self.array_layout.append(row_layout)
def analytical_power(self, corner, load): def analytical_power(self, corner, load):
"""Power of Bitcell array and bitline in nW.""" """Power of Bitcell array and bitline in nW."""

30
compiler/modules/bitcell_base_array.py
View File

@ -222,39 +222,17 @@ class bitcell_base_array(design.design):
yoffset += self.cell.height yoffset += self.cell.height
xoffset += self.cell.width xoffset += self.cell.width
else: else:
array_layout = []
for y in range(0,self.row_size):
row_layout = [] self.height = self.row_size * self.cell.height
alternate_bitcell = 1
alternate_strap = 1
for x in range(0,self.column_size):
if alternate_bitcell == 1:
row_layout.append(self.cell)
alternate_bitcell = 0
else:
row_layout.append(self.cell2)
alternate_bitcell = 1
if x != self.column_size:
if alternate_strap:
row_layout.append(self.strap2)
alternate_strap = 0
else:
row_layout.append(self.strap)
alternate_strap = 1
array_layout.append(row_layout)
self.height = self.row_size * self.cell.height + (self.row_size - 1) * self.strap.height
self.width = self.column_size * self.cell.width + (self.column_size-1) * self.strap.width self.width = self.column_size * self.cell.width + (self.column_size-1) * self.strap.width
yoffset = 0.0 yoffset = 0.0
for row in range(0, len(array_layout)): for row in range(0, len(self.array_layout)):
xoffset = 0.0 xoffset = 0.0
for col in range(0, len(array_layout[row])): for col in range(0, len(self.array_layout[row])):
inst = self.add_inst(name = "row_{}, col_{}".format(row,col), mod=array_layout[row][col]) inst = self.insts[col + row*len(self.array_layout[row])]
inst.place(offset=[xoffset, yoffset]) inst.place(offset=[xoffset, yoffset])
xoffset += inst.width xoffset += inst.width
yoffset += self.cell.height yoffset += self.cell.height