luke/OpenRAM
1
0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-30 09:58:33 +02:00
Code Issues Packages Projects Releases Wiki Activity

single port bitcell array done

Browse Source
This commit is contained in:
jcirimel
2020-09-16 05:46:14 -07:00
parent d22164bd48
commit 559dfbc7a6
2 changed files with 45 additions and 32 deletions
Download Patch File Download Diff File Expand all files Collapse all files
compiler/modules/bitcell_array.py
+41 -6
View File
@@ -73,12 +73,47 @@ class bitcell_array(bitcell_base_array):
def create_instances(self):
""" Create the module instances used in this design """
self.cell_inst = {}
for col in range(self.column_size):
for row in range(self.row_size):
name = "bit_r{0}_c{1}".format(row, col)
self.cell_inst[row, col]=self.add_inst(name=name,
mod=self.cell)
self.connect_inst(self.get_bitcell_pins(row, col))
if OPTS.tech_name != "sky130":
for col in range(self.column_size):
for row in range(self.row_size):
name = "bit_r{0}_c{1}".format(row, col)
self.cell_inst[row, col]=self.add_inst(name=name,
mod=self.cell)
self.connect_inst(self.get_bitcell_pins(row, col))
else:
self.array_layout = []
for row in range(0,self.row_size):
row_layout = []
alternate_bitcell = 1
alternate_strap = 1
for col in range(0,self.column_size):
if alternate_bitcell == 1:
row_layout.append(self.cell)
self.cell_inst[row, col]=self.add_inst(name="row_{}, col_{}_bitcell".format(row,col),
mod=self.cell)
alternate_bitcell = 0
else:
row_layout.append(self.cell2)
self.cell_inst[row, col]=self.add_inst(name="row_{}, col_{}_bitcell".format(row,col),
mod=self.cell2)
alternate_bitcell = 1
self.connect_inst(self.get_bitcell_pins(row, col))
if col != self.column_size-1:
if alternate_strap:
row_layout.append(self.strap2)
self.add_inst(name="row_{}, col_{}_wlstrap".format(row,col),
mod=self.strap2)
alternate_strap = 0
else:
row_layout.append(self.strap)
self.add_inst(name="row_{}, col_{}_wlstrap".format(row,col),
mod=self.strap)
alternate_strap = 1
self.connect_inst([])
self.array_layout.append(row_layout)
def analytical_power(self, corner, load):
"""Power of Bitcell array and bitline in nW."""