From 54e4d147f614abdae8d16d27682c46426a0b2365 Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 11 Jun 2020 15:03:50 -0700 Subject: [PATCH] Rail to ptx spacing based on routing layer not m1 --- compiler/pgates/pgate.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/pgates/pgate.py b/compiler/pgates/pgate.py index 67ba4a18..da359174 100644 --- a/compiler/pgates/pgate.py +++ b/compiler/pgates/pgate.py @@ -44,7 +44,7 @@ class pgate(design.design): self.route_layer_pitch = getattr(self, "{}_pitch".format(self.route_layer)) # This is the space from a S/D contact to the supply rail - contact_to_vdd_rail_space = 0.5 * self.m1_width + self.m1_space + contact_to_vdd_rail_space = 0.5 * self.route_layer_width + self.route_layer_space # This is a poly-to-poly of a flipped cell poly_to_poly_gate_space = self.poly_extend_active + 0.5 * self.poly_space