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Replaced cacti tech params with already existing params. Added an existence check in design_rules.

This commit is contained in:
Hunter Nichols 2021-07-27 14:31:22 -07:00
parent 1e08005639
commit 54cbef1aff
4 changed files with 21 additions and 10 deletions
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21
compiler/base/hierarchy_spice.py
View File

@ -17,7 +17,6 @@ from wire_spice_model import wire_spice_model
from power_data import power_data from power_data import power_data
import logical_effort import logical_effort
class spice(): class spice():
""" """
This provides a set of useful generic types for hierarchy This provides a set of useful generic types for hierarchy
@ -548,15 +547,25 @@ class spice():
w_folded_tr = width/folds w_folded_tr = width/folds
num_folded_tr = folds num_folded_tr = folds
# Re-created some logic contact to get minwidth as importing the contact
# module causes a failure
if "minwidth_contact" in tech.drc:
contact_width = tech.drc["minwidth_contact"]
elif "minwidth_active_contact" in tech.drc:
contact_width = tech.drc["minwidth_active_contact"]
else:
debug.warning("Undefined minwidth_contact in tech.")
contact_width = 0
# only for drain # only for drain
total_drain_w = (tech.spice["w_poly_contact"] + 2 * tech.drc["active_contact_to_gate"]) +\ total_drain_w = (contact_width + 2 * tech.drc["active_contact_to_gate"]) +\
(stack - 1) * tech.spice["spacing_poly_to_poly"] (stack - 1) * tech.drc["poly_to_poly"]
drain_h_for_sidewall = w_folded_tr drain_h_for_sidewall = w_folded_tr
total_drain_height_for_cap_wrt_gate = w_folded_tr + 2 * w_folded_tr * (stack - 1) total_drain_height_for_cap_wrt_gate = w_folded_tr + 2 * w_folded_tr * (stack - 1)
if num_folded_tr > 1: if num_folded_tr > 1:
total_drain_w += (num_folded_tr - 2) * (tech.spice["w_poly_contact"] + 2 * tech.drc["active_contact_to_gate"]) +\ total_drain_w += (num_folded_tr - 2) * (contact_width + 2 * tech.drc["active_contact_to_gate"]) +\
(num_folded_tr - 1) * ((stack - 1) * tech.spice["spacing_poly_to_poly"]) (num_folded_tr - 1) * ((stack - 1) * tech.drc["poly_to_poly"])
if num_folded_tr%2 == 0: if num_folded_tr%2 == 0:
drain_h_for_sidewall = 0 drain_h_for_sidewall = 0

6
compiler/drc/design_rules.py
View File

@ -34,6 +34,12 @@ class design_rules(dict):
""" """
self.rules[b] = c self.rules[b] = c
def __contains__(self, b):
"""
Allows checking existence of rules
"""
return b in self.rules
def __getitem__(self, b): def __getitem__(self, b):
""" """
For backward compatibility with existing rules. For backward compatibility with existing rules.

2
technology/freepdk45/tech/tech.py
View File

@ -468,8 +468,6 @@ spice["c_fringe"] = 0 # F/um, not defined in this technology
spice["cpolywire"] = 0 # F/um, replicated from CACTI which is hardcoded to 0 spice["cpolywire"] = 0 # F/um, replicated from CACTI which is hardcoded to 0
spice["c_junc"] = 5e-16 #F/um^2 spice["c_junc"] = 5e-16 #F/um^2
spice["c_junc_sw"] = 5e-16 #F/um spice["c_junc_sw"] = 5e-16 #F/um
spice["w_poly_contact"] = 0.065 # um
spice["spacing_poly_to_poly"] = 0.14 # um
spice["wire_c_per_um"] = 0 # Temp value spice["wire_c_per_um"] = 0 # Temp value
################################################### ###################################################

2
technology/scn4m_subm/tech/tech.py
View File

@ -415,8 +415,6 @@ spice["c_fringe"] = 0 # F/um, not defined in this technology
spice["cpolywire"] = 0 # F/um, replicated from CACTI which is hardcoded to 0 spice["cpolywire"] = 0 # F/um, replicated from CACTI which is hardcoded to 0
spice["c_junc"] = 9.276962e-16 #F/um^2 spice["c_junc"] = 9.276962e-16 #F/um^2
spice["c_junc_sw"] = 3.181055e-16 #F/um spice["c_junc_sw"] = 3.181055e-16 #F/um
spice["w_poly_contact"] = 2*_lambda_
spice["spacing_poly_to_poly"] = 3*_lambda_
spice["wire_c_per_um"] = 0 # Temp value spice["wire_c_per_um"] = 0 # Temp value
################################################### ###################################################