From 54cbef1aff18afa957104f8ee414f4096db2c5fe Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Tue, 27 Jul 2021 14:31:22 -0700 Subject: [PATCH] Replaced cacti tech params with already existing params. Added an existence check in design_rules. --- compiler/base/hierarchy_spice.py | 21 +++++++++++++++------ compiler/drc/design_rules.py | 6 ++++++ technology/freepdk45/tech/tech.py | 2 -- technology/scn4m_subm/tech/tech.py | 2 -- 4 files changed, 21 insertions(+), 10 deletions(-) diff --git a/compiler/base/hierarchy_spice.py b/compiler/base/hierarchy_spice.py index b594d004..539b8f77 100644 --- a/compiler/base/hierarchy_spice.py +++ b/compiler/base/hierarchy_spice.py @@ -17,7 +17,6 @@ from wire_spice_model import wire_spice_model from power_data import power_data import logical_effort - class spice(): """ This provides a set of useful generic types for hierarchy @@ -548,15 +547,25 @@ class spice(): w_folded_tr = width/folds num_folded_tr = folds - + + # Re-created some logic contact to get minwidth as importing the contact + # module causes a failure + if "minwidth_contact" in tech.drc: + contact_width = tech.drc["minwidth_contact"] + elif "minwidth_active_contact" in tech.drc: + contact_width = tech.drc["minwidth_active_contact"] + else: + debug.warning("Undefined minwidth_contact in tech.") + contact_width = 0 + # only for drain - total_drain_w = (tech.spice["w_poly_contact"] + 2 * tech.drc["active_contact_to_gate"]) +\ - (stack - 1) * tech.spice["spacing_poly_to_poly"] + total_drain_w = (contact_width + 2 * tech.drc["active_contact_to_gate"]) +\ + (stack - 1) * tech.drc["poly_to_poly"] drain_h_for_sidewall = w_folded_tr total_drain_height_for_cap_wrt_gate = w_folded_tr + 2 * w_folded_tr * (stack - 1) if num_folded_tr > 1: - total_drain_w += (num_folded_tr - 2) * (tech.spice["w_poly_contact"] + 2 * tech.drc["active_contact_to_gate"]) +\ - (num_folded_tr - 1) * ((stack - 1) * tech.spice["spacing_poly_to_poly"]) + total_drain_w += (num_folded_tr - 2) * (contact_width + 2 * tech.drc["active_contact_to_gate"]) +\ + (num_folded_tr - 1) * ((stack - 1) * tech.drc["poly_to_poly"]) if num_folded_tr%2 == 0: drain_h_for_sidewall = 0 diff --git a/compiler/drc/design_rules.py b/compiler/drc/design_rules.py index 8ffcf329..56d0e8b6 100644 --- a/compiler/drc/design_rules.py +++ b/compiler/drc/design_rules.py @@ -34,6 +34,12 @@ class design_rules(dict): """ self.rules[b] = c + def __contains__(self, b): + """ + Allows checking existence of rules + """ + return b in self.rules + def __getitem__(self, b): """ For backward compatibility with existing rules. diff --git a/technology/freepdk45/tech/tech.py b/technology/freepdk45/tech/tech.py index 6fb57a4e..cf75ff54 100644 --- a/technology/freepdk45/tech/tech.py +++ b/technology/freepdk45/tech/tech.py @@ -468,8 +468,6 @@ spice["c_fringe"] = 0 # F/um, not defined in this technology spice["cpolywire"] = 0 # F/um, replicated from CACTI which is hardcoded to 0 spice["c_junc"] = 5e-16 #F/um^2 spice["c_junc_sw"] = 5e-16 #F/um -spice["w_poly_contact"] = 0.065 # um -spice["spacing_poly_to_poly"] = 0.14 # um spice["wire_c_per_um"] = 0 # Temp value ################################################### diff --git a/technology/scn4m_subm/tech/tech.py b/technology/scn4m_subm/tech/tech.py index 0c94dee8..29ed1332 100644 --- a/technology/scn4m_subm/tech/tech.py +++ b/technology/scn4m_subm/tech/tech.py @@ -415,8 +415,6 @@ spice["c_fringe"] = 0 # F/um, not defined in this technology spice["cpolywire"] = 0 # F/um, replicated from CACTI which is hardcoded to 0 spice["c_junc"] = 9.276962e-16 #F/um^2 spice["c_junc_sw"] = 3.181055e-16 #F/um -spice["w_poly_contact"] = 2*_lambda_ -spice["spacing_poly_to_poly"] = 3*_lambda_ spice["wire_c_per_um"] = 0 # Temp value ###################################################