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Rework precharge route supply horizontally

This commit is contained in:
mrg 2022-02-28 11:36:10 -08:00
parent 8b4ef9b6c1
commit 54bd022efc
2 changed files with 22 additions and 26 deletions
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13
compiler/base/hierarchy_layout.py
View File

@ -434,23 +434,24 @@ class layout():
inst = self.local_insts[i] inst = self.local_insts[i]
for pin in inst.get_pins(name): for pin in inst.get_pins(name):
try: try:
bins[pin.cy()].append(pin) bins[pin.cy()].append((inst,pin))
except KeyError: except KeyError:
bins[pin.cy()] = [pin] bins[pin.cy()] = [(inst,pin)]
for y, v in bins.items(): for y, v in bins.items():
left_x = min([x.lx() for x in v]) left_x = min([inst.lx() for (inst,pin) in v])
right_x = max([x.rx() for x in v]) right_x = max([inst.rx() for (inst,pin) in v])
last_via = None last_via = None
for pin in v: for inst,pin in v:
if layer: if layer:
pin_layer = layer pin_layer = layer
else: else:
pin_layer = self.supply_stack[0] pin_layer = self.supply_stack[0]
last_via = self.add_via_stack_center(from_layer=pin.layer, last_via = self.add_via_stack_center(from_layer=pin.layer,
to_layer=pin_layer, to_layer=pin_layer,
offset=pin.center()) offset=pin.center(),
min_area=True)
if last_via: if last_via:
via_height=last_via.mod.second_layer_height via_height=last_via.mod.second_layer_height

35
compiler/pgates/precharge.py
View File

@ -71,7 +71,7 @@ class precharge(design.design):
self.connect_poly() self.connect_poly()
self.route_en() self.route_en()
self.place_nwell_and_contact() self.place_nwell_and_contact()
self.route_vdd_rail() self.route_vdd()
self.route_bitlines() self.route_bitlines()
self.connect_to_bitlines() self.connect_to_bitlines()
self.add_boundary() self.add_boundary()
@ -91,34 +91,29 @@ class precharge(design.design):
mults=self.ptx_mults, mults=self.ptx_mults,
tx_type="pmos") tx_type="pmos")
def route_vdd_rail(self): def route_vdd(self):
""" """
Adds a vdd rail at the top of the cell Adds a vdd rail at the top of the cell
""" """
# Adds the rail across the width of the cell
vdd_position = vector(0.5 * self.width, self.height)
layer_width = drc("minwidth_" + self.en_layer)
self.add_rect_center(layer=self.en_layer,
offset=vdd_position,
width=self.width,
height=layer_width)
pmos_pin = self.upper_pmos2_inst.get_pin("S") pmos_pin = self.upper_pmos2_inst.get_pin("S")
pmos_pos = pmos_pin.center()
# center of vdd rail self.add_path(pmos_pin.layer, [pmos_pos, self.well_contact_pos])
pmos_vdd_pos = vector(pmos_pin.cx(), vdd_position.y)
self.add_path(self.en_layer, [pmos_pin.center(), pmos_vdd_pos])
self.add_power_pin("vdd",
self.well_contact_pos,
directions=("V", "V"))
self.add_via_stack_center(from_layer=pmos_pin.layer, self.add_via_stack_center(from_layer=pmos_pin.layer,
to_layer=self.en_layer, to_layer=self.supply_stack[0],
offset=pmos_pin.center(), offset=self.well_contact_pos,
directions=("V", "V")) directions=("V", "V"))
self.add_min_area_rect_center(layer=self.en_layer,
offset=self.well_contact_pos,
width=self.well_contact.mod.second_layer_width)
self.add_layout_pin_rect_center(text="vdd",
layer=self.supply_stack[0],
offset=self.well_contact_pos)
def create_ptx(self): def create_ptx(self):
""" """
Create both the upper_pmos and lower_pmos to the module Create both the upper_pmos and lower_pmos to the module