diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py
index 5adc163a..0ff95483 100644
--- a/compiler/base/hierarchy_layout.py
+++ b/compiler/base/hierarchy_layout.py
@@ -434,23 +434,24 @@ class layout():
             inst = self.local_insts[i]
             for pin in inst.get_pins(name):
                 try:
-                    bins[pin.cy()].append(pin)
+                    bins[pin.cy()].append((inst,pin))
                 except KeyError:
-                    bins[pin.cy()] = [pin]
+                    bins[pin.cy()] = [(inst,pin)]
 
         for y, v in bins.items():
-            left_x = min([x.lx() for x in v])
-            right_x = max([x.rx() for x in v])
+            left_x = min([inst.lx() for (inst,pin) in v])
+            right_x = max([inst.rx() for (inst,pin) in v])
 
             last_via = None
-            for pin in v:
+            for inst,pin in v:
                 if layer:
                     pin_layer = layer
                 else:
                     pin_layer = self.supply_stack[0]
                 last_via = self.add_via_stack_center(from_layer=pin.layer,
                                                      to_layer=pin_layer,
-                                                     offset=pin.center())
+                                                     offset=pin.center(),
+                                                     min_area=True)
 
             if last_via:
                 via_height=last_via.mod.second_layer_height
diff --git a/compiler/pgates/precharge.py b/compiler/pgates/precharge.py
index 2042dc7c..aa1f1a70 100644
--- a/compiler/pgates/precharge.py
+++ b/compiler/pgates/precharge.py
@@ -71,7 +71,7 @@ class precharge(design.design):
         self.connect_poly()
         self.route_en()
         self.place_nwell_and_contact()
-        self.route_vdd_rail()
+        self.route_vdd()
         self.route_bitlines()
         self.connect_to_bitlines()
         self.add_boundary()
@@ -91,34 +91,29 @@ class precharge(design.design):
                                    mults=self.ptx_mults,
                                    tx_type="pmos")
 
-    def route_vdd_rail(self):
+    def route_vdd(self):
         """
         Adds a vdd rail at the top of the cell
         """
 
-        # Adds the rail across the width of the cell
-        vdd_position = vector(0.5 * self.width, self.height)
-        layer_width = drc("minwidth_" + self.en_layer)
-        self.add_rect_center(layer=self.en_layer,
-                             offset=vdd_position,
-                             width=self.width,
-                             height=layer_width)
-
         pmos_pin = self.upper_pmos2_inst.get_pin("S")
-
-        # center of vdd rail
-        pmos_vdd_pos = vector(pmos_pin.cx(), vdd_position.y)
-        self.add_path(self.en_layer, [pmos_pin.center(), pmos_vdd_pos])
-
-        self.add_power_pin("vdd",
-                           self.well_contact_pos,
-                           directions=("V", "V"))
+        pmos_pos = pmos_pin.center()
+        self.add_path(pmos_pin.layer, [pmos_pos, self.well_contact_pos])
 
         self.add_via_stack_center(from_layer=pmos_pin.layer,
-                                  to_layer=self.en_layer,
-                                  offset=pmos_pin.center(),
+                                  to_layer=self.supply_stack[0],
+                                  offset=self.well_contact_pos,
                                   directions=("V", "V"))
 
+        self.add_min_area_rect_center(layer=self.en_layer,
+                                      offset=self.well_contact_pos,
+                                      width=self.well_contact.mod.second_layer_width)
+
+        self.add_layout_pin_rect_center(text="vdd",
+                                        layer=self.supply_stack[0],
+                                        offset=self.well_contact_pos)
+
+
     def create_ptx(self):
         """
         Create both the upper_pmos and lower_pmos to the module