luke/OpenRAM
1
0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 01:24:39 +02:00
Code Issues Packages Projects Releases Wiki Activity

parameterize how power ring is connected to crba

Browse Source
This commit is contained in:
Jesse Cirimelli-Low
2026-05-06 09:50:56 -07:00
parent 28fef79202
commit 541d4ff572
6 changed files with 54 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files
compiler/modules/capped_replica_bitcell_array.py
+5 -4
View File
@@ -10,6 +10,7 @@ from openram.base import contact
from openram.sram_factory import factory
from openram.tech import drc, spice
from openram.tech import cell_properties as props
from openram.tech import connect_ring_bottom, connect_ring_left, connect_ring_right, connect_ring_top
from openram import OPTS
from .bitcell_base_array import bitcell_base_array
@@ -338,10 +339,10 @@ class capped_replica_bitcell_array(bitcell_base_array):
bitcell = factory.create(module_type="pbitcell")
else:
bitcell = getattr(props, "bitcell_{}port".format(OPTS.num_ports))
top = True
bottom = True
left = False
right = False
top = connect_ring_top
bottom = connect_ring_bottom
left = connect_ring_left
right = connect_ring_right
if top:
inst = self.dummy_row_insts[1]
compiler/modules/dummy_array.py
+6 -3
View File
@@ -64,9 +64,12 @@ class dummy_array(bitcell_base_array):
core_block[(1 + r) % 2][(0+c) %2] = geometry.instance(f"core_{(1 + r)%2}_{(0+c)%2}", mod=self.dummy_cell, is_bitcell=True, mirror='MX')
core_block[(1 + r) % 2][(1+c) %2] = geometry.instance(f"core_{(1 + r)%2}_{(1+c)%2}", mod=self.dummy_cell, is_bitcell=True, mirror='XY')
else:
core_block = [[0 for x in range(1)] for y in range(2)]
core_block[(0 + self.row_offset) % 2][(0+self.column_offset) %2] = geometry.instance("core_0_0", mod=self.dummy_cell, is_bitcell=True)
core_block[(1 + self.row_offset) % 2][(0+self.column_offset) %2] = geometry.instance("core_1_0", mod=self.dummy_cell, is_bitcell=True, mirror='MX')
core_block = [[0 for x in range(1)] for y in range(2)]
core_block[(0 + r) % 2][0] = geometry.instance("core_0_0", mod=self.dummy_cell, is_bitcell=True)
core_block[(1 + r) % 2][0] = geometry.instance("core_1_0", mod=self.dummy_cell, is_bitcell=True, mirror='MX')
print(core_block)
#print(r, c)
#print(core_block)