From 541d4ff572f333c3ed42630cfb65f592a3df862e Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Wed, 6 May 2026 09:50:56 -0700 Subject: [PATCH] parameterize how power ring is connected to crba --- compiler/modules/capped_replica_bitcell_array.py | 9 +++++---- compiler/modules/dummy_array.py | 9 ++++++--- technology/freepdk45/tech/tech.py | 13 +++++++++++++ technology/scn4m_subm/tech/tech.py | 15 +++++++++++++++ .../sky130/tech/tech_configs/tech_custom_cell.py | 8 ++++++++ .../sky130/tech/tech_configs/tech_cypress_cell.py | 7 +++++++ 6 files changed, 54 insertions(+), 7 deletions(-) diff --git a/compiler/modules/capped_replica_bitcell_array.py b/compiler/modules/capped_replica_bitcell_array.py index d87ad247..4ee5e914 100644 --- a/compiler/modules/capped_replica_bitcell_array.py +++ b/compiler/modules/capped_replica_bitcell_array.py @@ -10,6 +10,7 @@ from openram.base import contact from openram.sram_factory import factory from openram.tech import drc, spice from openram.tech import cell_properties as props +from openram.tech import connect_ring_bottom, connect_ring_left, connect_ring_right, connect_ring_top from openram import OPTS from .bitcell_base_array import bitcell_base_array @@ -338,10 +339,10 @@ class capped_replica_bitcell_array(bitcell_base_array): bitcell = factory.create(module_type="pbitcell") else: bitcell = getattr(props, "bitcell_{}port".format(OPTS.num_ports)) - top = True - bottom = True - left = False - right = False + top = connect_ring_top + bottom = connect_ring_bottom + left = connect_ring_left + right = connect_ring_right if top: inst = self.dummy_row_insts[1] diff --git a/compiler/modules/dummy_array.py b/compiler/modules/dummy_array.py index b6b72913..a441690f 100644 --- a/compiler/modules/dummy_array.py +++ b/compiler/modules/dummy_array.py @@ -64,9 +64,12 @@ class dummy_array(bitcell_base_array): core_block[(1 + r) % 2][(0+c) %2] = geometry.instance(f"core_{(1 + r)%2}_{(0+c)%2}", mod=self.dummy_cell, is_bitcell=True, mirror='MX') core_block[(1 + r) % 2][(1+c) %2] = geometry.instance(f"core_{(1 + r)%2}_{(1+c)%2}", mod=self.dummy_cell, is_bitcell=True, mirror='XY') else: - core_block = [[0 for x in range(1)] for y in range(2)] - core_block[(0 + self.row_offset) % 2][(0+self.column_offset) %2] = geometry.instance("core_0_0", mod=self.dummy_cell, is_bitcell=True) - core_block[(1 + self.row_offset) % 2][(0+self.column_offset) %2] = geometry.instance("core_1_0", mod=self.dummy_cell, is_bitcell=True, mirror='MX') + core_block = [[0 for x in range(1)] for y in range(2)] + core_block[(0 + r) % 2][0] = geometry.instance("core_0_0", mod=self.dummy_cell, is_bitcell=True) + core_block[(1 + r) % 2][0] = geometry.instance("core_1_0", mod=self.dummy_cell, is_bitcell=True, mirror='MX') + + print(core_block) + #print(r, c) #print(core_block) diff --git a/technology/freepdk45/tech/tech.py b/technology/freepdk45/tech/tech.py index 283f6faf..ea838fac 100644 --- a/technology/freepdk45/tech/tech.py +++ b/technology/freepdk45/tech/tech.py @@ -33,11 +33,21 @@ tech_modules = d.module_type() ################################################### cell_properties = d.cell_properties() +cell_properties.bitcell_1port.mirror.y = True +cell_properties.bitcell_1port.mirror.y = False + +cell_properties.bitcell_2port.mirror.y = True +cell_properties.bitcell_2port.mirror.y = False + ################################################### # Custom cell properties ################################################### layer_properties = d.layer_properties() +connect_ring_top = False +connect_ring_bottom = False +connect_ring_left = True +connect_ring_right = True ################################################### # GDS file info ################################################### @@ -94,6 +104,9 @@ preferred_directions = {"poly": "V", "m2": "V", "m3": "H", "m4": "V"} + +lef_rom_interconnect = ["m1", "m2", "m3", "m4"] + ################################################### # Power grid ################################################### diff --git a/technology/scn4m_subm/tech/tech.py b/technology/scn4m_subm/tech/tech.py index b5a50d9c..7c4381f0 100644 --- a/technology/scn4m_subm/tech/tech.py +++ b/technology/scn4m_subm/tech/tech.py @@ -34,6 +34,12 @@ cell_properties = d.cell_properties() cell_properties.bitcell_1port.gnd_layer = "m2" cell_properties.bitcell_1port.gnd_dir = "V" +cell_properties.bitcell_1port.mirror.y = True +cell_properties.bitcell_1port.mirror.y = False + +cell_properties.bitcell_2port.mirror.y = True +cell_properties.bitcell_2port.mirror.y = False + ################################################### # Custom cell properties ################################################### @@ -92,12 +98,19 @@ preferred_directions = {"poly": "V", "m3": "H", "m4": "V"} +lef_rom_interconnect = ["m1", "m2", "m3", "m4"] + + ################################################### # Power grid ################################################### # Use M3/M4 power_grid = m3_stack +connect_ring_top = False +connect_ring_bottom = False +connect_ring_left = True +connect_ring_right = True ################################################### ##GDS Layer Map ################################################### @@ -340,6 +353,8 @@ drc.add_enclosure("m4", layer = "via3", enclosure = 2*_lambda_) + + ################################################### # Spice Simulation Parameters ################################################### diff --git a/technology/sky130/tech/tech_configs/tech_custom_cell.py b/technology/sky130/tech/tech_configs/tech_custom_cell.py index b797cc64..a793a9bd 100644 --- a/technology/sky130/tech/tech_configs/tech_custom_cell.py +++ b/technology/sky130/tech/tech_configs/tech_custom_cell.py @@ -245,6 +245,14 @@ cell_properties.names["write_driver"] = "sky130_fd_bd_sram__openram_write_driver array_row_multiple = 2 array_col_multiple = 2 +################################################### +# Power grid +################################################### +connect_ring_top = True +connect_ring_bottom = True +connect_ring_left = False +connect_ring_right = False + ################################################### # Custom layer properties ################################################### diff --git a/technology/sky130/tech/tech_configs/tech_cypress_cell.py b/technology/sky130/tech/tech_configs/tech_cypress_cell.py index e3e10617..ea13cd66 100644 --- a/technology/sky130/tech/tech_configs/tech_cypress_cell.py +++ b/technology/sky130/tech/tech_configs/tech_cypress_cell.py @@ -273,6 +273,13 @@ layer_properties.wordline_driver.vertical_supply = True layer_properties.global_wordline_layer = "m5" +################################################### +# Power grid +################################################### +connect_ring_top = True +connect_ring_bottom = True +connect_ring_left = False +connect_ring_right = False ################################################### # Discrete tx bins