From 54120f8405d02713fb73ab698cd22e278c266866 Mon Sep 17 00:00:00 2001
From: mrg <mrg@ucsc.edu>
Date: Mon, 22 Jun 2020 12:35:37 -0700
Subject: [PATCH] Add option for removing subckt/instances of cells for row/col
 caps

---
 compiler/base/hierarchy_spice.py            | 9 ++++++++-
 compiler/bitcells/col_cap_bitcell_1rw_1r.py | 1 +
 compiler/bitcells/row_cap_bitcell_1rw_1r.py | 1 +
 3 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/compiler/base/hierarchy_spice.py b/compiler/base/hierarchy_spice.py
index 0e41c4b0..5ba60435 100644
--- a/compiler/base/hierarchy_spice.py
+++ b/compiler/base/hierarchy_spice.py
@@ -40,6 +40,8 @@ class spice():
         # THE CONNECTIONS MUST MATCH THE ORDER OF THE PINS (restriction imposed by the
         # Spice format)
         self.conns = []
+        # If this is set, it will out output subckt or isntances of this (for row/col caps etc.)
+        self.no_instances = False
         # Keep track of any comments to add the the spice
         try:
             self.commments
@@ -264,7 +266,9 @@ class spice():
         Writes the spice subcircuit from the library or the dynamically generated one
         """
 
-        if not self.spice:
+        if self.no_instances:
+            return
+        elif not self.spice:
             # If spice isn't defined, we dynamically generate one.
             
             # recursively write the modules
@@ -303,6 +307,9 @@ class spice():
                 # these are wires and paths
                 if self.conns[i] == []:
                     continue
+                # Instance with no devices in it needs no subckt/instance
+                if self.insts[i].mod.no_instances:
+                    continue
                 if lvs_netlist and hasattr(self.insts[i].mod, "lvs_device"):
                     sp.write(self.insts[i].mod.lvs_device.format(self.insts[i].name,
                                                                    " ".join(self.conns[i])))
diff --git a/compiler/bitcells/col_cap_bitcell_1rw_1r.py b/compiler/bitcells/col_cap_bitcell_1rw_1r.py
index 315ad23f..01818a12 100644
--- a/compiler/bitcells/col_cap_bitcell_1rw_1r.py
+++ b/compiler/bitcells/col_cap_bitcell_1rw_1r.py
@@ -41,3 +41,4 @@ class col_cap_bitcell_1rw_1r(bitcell_base.bitcell_base):
         self.height = col_cap_bitcell_1rw_1r.height
         self.pin_map = col_cap_bitcell_1rw_1r.pin_map
         self.add_pin_types(self.type_list)
+        self.no_instances = True
diff --git a/compiler/bitcells/row_cap_bitcell_1rw_1r.py b/compiler/bitcells/row_cap_bitcell_1rw_1r.py
index b50629f0..f7a3a687 100644
--- a/compiler/bitcells/row_cap_bitcell_1rw_1r.py
+++ b/compiler/bitcells/row_cap_bitcell_1rw_1r.py
@@ -41,3 +41,4 @@ class row_cap_bitcell_1rw_1r(bitcell_base.bitcell_base):
         self.height = row_cap_bitcell_1rw_1r.height
         self.pin_map = row_cap_bitcell_1rw_1r.pin_map
         self.add_pin_types(self.type_list)
+        self.no_instances = True