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https://github.com/VLSIDA/OpenRAM.git
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checkpoint from tt submission
This commit is contained in:
Jesse Cirimelli-Low
@@ -15,19 +15,11 @@ class sky130_col_cap(design):
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def __init__(self, version, name="",left_rbl=[],right_rbl=[]):
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if version == "colend":
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if OPTS.control_logic == "control_logic_delay" or not right_rbl:
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cell_name = "sky130_fd_bd_sram__sram_sp_colend"
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else:
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cell_name = "sky130_fd_bd_sram__openram_sp_colend_replica"
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cell_name = "sky130_fd_bd_sram__sram_sp_colend"
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prop = props.col_cap_1port_bitcell
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elif version == "colenda":
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if OPTS.control_logic == "control_logic_delay" or not left_rbl:
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cell_name = "sky130_fd_bd_sram__sram_sp_colenda"
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else:
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cell_name = "sky130_fd_bd_sram__openram_sp_colenda_replica"
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cell_name = "sky130_fd_bd_sram__sram_sp_colenda"
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prop = props.col_cap_1port_bitcell
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elif version == "colend_p_cent":
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cell_name = "sky130_fd_bd_sram__sram_sp_colend_p_cent"
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prop = props.col_cap_1port_strap_ground
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@@ -41,5 +33,5 @@ class sky130_col_cap(design):
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cell_name = "sky130_fd_bd_sram__sram_sp_colenda_cent"
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prop = props.col_cap_1port_strap_power
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else:
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debug.error("Invalid type for col_end", -1)
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debug.error("Invalid type for col_end: {}".format(version), -1)
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super().__init__(name=name, cell_name=cell_name, prop=prop)
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@@ -17,7 +17,7 @@ class sky130_row_cap_array(row_cap_array, sky130_bitcell_base_array):
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"""
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Generate a dummy row/column for the replica array.
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"""
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def __init__(self, rows, cols, column_offset=0, mirror=0, location="", name=""):
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def __init__(self, rows, cols, column_offset=0, row_offset=0, mirror=0, location="", name=""):
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super().__init__(rows, cols, column_offset=column_offset, location=location, name=name)
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self.mirror = mirror
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self.location = location
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@@ -24,6 +24,7 @@ File containing the process technology parameters for Skywater 130nm.
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# For example: tech_modules["contact"] = "contact_freepdk45"
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tech_modules = d.module_type()
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# These modules have been hand designed and provided in this repository.
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tech_modules["nand2_dec"] = "nand2_dec"
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tech_modules["nand3_dec"] = "nand3_dec"
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@@ -33,23 +34,24 @@ tech_modules["nand4_dec"] = "nand4_dec"
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# These are for single port and dual port as a list,
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# or for both if there is no list,
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# or only applicable to one if there is no list.
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tech_modules["bitcell_1port"] = "sky130_bitcell"
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tech_modules["replica_bitcell_1port"] = "sky130_replica_bitcell"
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tech_modules["dummy_bitcell_1port"] = "sky130_dummy_bitcell"
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#tech_modules["bitcell_1port"] = "sky130_bitcell"
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#tech_modules["replica_bitcell_1port"] = "sky130_replica_bitcell"
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#tech_modules["dummy_bitcell_1port"] = "sky130_dummy_bitcell"
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tech_modules["replica_bitcell_2port"] = "replica_bitcell_2port"
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tech_modules["dummy_bitcell_2port"] = "dummy_bitcell_2port"
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tech_modules["bitcell_2port"] = "bitcell_2port"
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tech_modules["bitcell_array"] = ["sky130_bitcell_array", "bitcell_array"]
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tech_modules["replica_bitcell_array"] = ["sky130_replica_bitcell_array", "replica_bitcell_array"]
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tech_modules["capped_replica_bitcell_array"] = ["sky130_capped_replica_bitcell_array", "capped_replica_bitcell_array"]
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tech_modules["dummy_array"] = ["sky130_dummy_array", "dummy_array"]
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tech_modules["bitcell_array"] = ["bitcell_array", "bitcell_array"]
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tech_modules["replica_bitcell_array"] = ["replica_bitcell_array", "replica_bitcell_array"]
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tech_modules["capped_replica_bitcell_array"] = ["capped_replica_bitcell_array", "capped_replica_bitcell_array"]
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tech_modules["dummy_array"] = ["dummy_array", "dummy_array"]
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tech_modules["replica_column"] = ["sky130_replica_column", "replica_column"]
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tech_modules["replica_column"] = ["replica_column", "replica_column"]
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tech_modules["col_cap_array"] = ["sky130_col_cap_array", "col_cap_array"]
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tech_modules["col_cap"] = ["sky130_col_cap", "col_cap_bitcell_2port"]
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tech_modules["col_cap_array"] = ["col_cap_array", "col_cap_array"]
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tech_modules["col_cap"] = ["col_cap_bitcell_1port", "col_cap_bitcell_2port"]
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tech_modules["corner"] = ["sky130_corner", None]
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tech_modules["internal"] = ["sky130_internal", None]
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tech_modules["row_cap_array"] = ["sky130_row_cap_array", "row_cap_array"]
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@@ -68,28 +70,32 @@ tech_modules["and4_dec"] = "and4_dec"
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###################################################
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cell_properties = d.cell_properties()
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cell_properties.bitcell_power_pin_directions = ("H", "H")
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cell_properties.power_name = 'VPWR'
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cell_properties.ground_name = 'VGND'
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cell_properties.bitcell_power_pin_directions = ("V", "V")
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cell_properties.bitcell_1port.mirror.x = True
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cell_properties.bitcell_1port.mirror.y = True
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cell_properties.bitcell_1port.end_caps = True
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cell_properties.bitcell_1port.boundary_layer = "mem"
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cell_properties.bitcell_1port.port_order = ['bl', 'br', 'gnd', 'vdd', 'vpb', 'vnb', 'wl']
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cell_properties.bitcell_1port.port_types = ["OUTPUT", "OUTPUT", "GROUND", "POWER", "BIAS", "BIAS", "INPUT"]
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cell_properties.bitcell_1port.end_caps = False
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cell_properties.bitcell_1port.boundary_layer = "boundary"
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cell_properties.bitcell_1port.port_order = ['bl', 'br', 'wl', 'vdd', 'gnd']
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cell_properties.bitcell_1port.port_types = ["INPUT", "INPUT", "GROUND", "POWER", "OUTPUT"]
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cell_properties.bitcell_1port.port_map = {'bl': 'BL',
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'br': 'BR',
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'wl': 'WL',
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'gnd': 'VGND',
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'vdd': 'VPWR',
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'vnb': 'VNB',
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'vpb': 'VPB',
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'gnd': 'VGND'}
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'wl': 'WL'}
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cell_properties.bitcell_1port.wl_layer = "m2"
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cell_properties.bitcell_1port.bl_layer = "m1"
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cell_properties.bitcell_1port.vdd_layer = "m1"
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cell_properties.bitcell_1port.vdd_dir = "V"
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cell_properties.bitcell_1port.gnd_layer = "m2"
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cell_properties.bitcell_1port.gnd_dir = "H"
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cell_properties.bitcell_1port.gnd_layer = "m1"
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cell_properties.bitcell_1port.gnd_dir = "V"
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cell_properties.bitcell_2port.mirror.x = True
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cell_properties.bitcell_2port.mirror.y = True
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@@ -103,47 +109,45 @@ cell_properties.bitcell_2port.port_map = {'bl0': 'BL0',
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'wl1': 'WL1',
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'vdd': 'VDD',
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'gnd': 'GND'}
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cell_properties.bitcell_1port.wl_layer = "m2"
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cell_properties.bitcell_1port.vdd_layer = "m2"
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cell_properties.bitcell_1port.vdd_dir = "H"
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cell_properties.bitcell_1port.gnd_layer = "m2"
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cell_properties.bitcell_1port.gnd_dir = "H"
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cell_properties.bitcell_1port.vdd_layer = "m1"
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cell_properties.bitcell_1port.vdd_dir = "V"
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cell_properties.bitcell_1port.gnd_layer = "m1"
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cell_properties.bitcell_1port.gnd_dir = "V"
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cell_properties.bitcell_2port.wl_layer = "m2"
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cell_properties.bitcell_2port.vdd_layer = "m1"
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cell_properties.bitcell_2port.vdd_dir = "H"
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cell_properties.bitcell_2port.gnd_layer = "m2"
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cell_properties.bitcell_2port.gnd_dir = "H"
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cell_properties.col_cap_1port_bitcell = d.cell(['bl', 'br', 'vdd', 'gnd', 'vpb', 'vnb', 'gate'],
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['INPUT', 'INPUT','POWER', 'GROUND', 'BIAS', 'BIAS', 'INPUT'],
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cell_properties.col_cap_1port_bitcell = d.cell(['bl', 'br', 'vdd', 'gnd',],
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['INPUT', 'INPUT','POWER', 'GROUND', ],
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{'bl': 'bl',
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'br': 'br',
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'vdd': 'vdd',
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'gnd': 'gnd',
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'vnb': 'vnb',
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'vpb': 'vpb',
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'gate': 'gate'})
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cell_properties.col_cap_1port_bitcell.boundary_layer = "mem"
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'gnd': 'gnd',})
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cell_properties.col_cap_1port_bitcell.boundary_layer = "boundary"
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cell_properties.col_cap_1port_strap_power = d.cell(['vdd', 'vpb', 'vnb'],
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['POWER', 'BIAS', 'BIAS'],
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{'vnb': 'VNB',
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'vpb': 'VPB',
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'vdd': 'VPWR'})
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cell_properties.col_cap_1port_strap_power.boundary_layer = "mem"
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cell_properties.col_cap_1port_strap_power.boundary_layer = "boundary"
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cell_properties.col_cap_1port_strap_ground = d.cell(['gnd', 'vpb', 'vnb'],
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['GROUND', 'BIAS', 'BIAS'],
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{'vnb': 'VNB',
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'vpb': 'VPB',
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'gnd': 'VGND'})
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cell_properties.col_cap_1port_strap_ground.boundary_layer = "mem"
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cell_properties.col_cap_1port_strap_ground.boundary_layer = "boundary"
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cell_properties.row_cap_1port_cell = d.cell(['vdd', 'wl'],
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['POWER', 'INPUT'],
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{'wl': 'WL',
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'vdd': 'VPWR'})
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cell_properties.row_cap_1port_cell.boundary_layer = "mem"
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cell_properties.row_cap_1port_cell.boundary_layer = "boundary"
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cell_properties.col_cap_2port.port_order = ['bl0', 'br0', 'bl1', 'br1', 'vdd']
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cell_properties.col_cap_2port.port_map = {'bl0': 'BL0',
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@@ -163,7 +167,7 @@ cell_properties.ptx.model_is_subckt = True
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cell_properties.pgate.add_implants = True
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cell_properties.use_strap = True
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cell_properties.use_strap = False
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cell_properties.strap_module = "internal"
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cell_properties.strap_version = "wlstrap"
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@@ -219,9 +223,13 @@ cell_properties.write_driver.port_map = {'din': 'DIN',
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# If it is a list, the first is single port and the second is dual port.
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# If it is string, it is used for both single and dual port.
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cell_properties.names["dff"] = "sky130_fd_bd_sram__openram_dff"
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cell_properties.names["nand2_dec"] = ["sky130_fd_bd_sram__openram_sp_nand2_dec", "sky130_fd_bd_sram__openram_dp_nand2_dec"]
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cell_properties.names["nand3_dec"] = ["sky130_fd_bd_sram__openram_sp_nand3_dec", "sky130_fd_bd_sram__openram_dp_nand3_dec"]
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cell_properties.names["nand4_dec"] = ["sky130_fd_bd_sram__openram_sp_nand4_dec", "sky130_fd_bd_sram__openram_dp_nand4_dec"]
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cell_properties.names["nand2_dec"] = ["sky130_fd_bd_sram__openram_dp_nand2_dec", "sky130_fd_bd_sram__openram_dp_nand2_dec"]
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cell_properties.names["nand3_dec"] = ["sky130_fd_bd_sram__openram_dp_nand3_dec", "sky130_fd_bd_sram__openram_dp_nand3_dec"]
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cell_properties.names["nand4_dec"] = ["sky130_fd_bd_sram__openram_dp_nand4_dec", "sky130_fd_bd_sram__openram_dp_nand4_dec"]
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cell_properties.names["bitcell_1port"] = "sky130_custom_cell"
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cell_properties.names["replica_bitcell_1port"] = "sky130_custom_replica"
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cell_properties.names["dummy_bitcell_1port"] = "sky130_custom_dummy"
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cell_properties.names["bitcell_2port"] = "sky130_fd_bd_sram__openram_dp_cell"
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cell_properties.names["dummy_bitcell_2port"] = "sky130_fd_bd_sram__openram_dp_cell_dummy"
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@@ -253,7 +261,7 @@ layer_properties.hierarchical_predecode.input_layer = "li"
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layer_properties.hierarchical_predecode.output_layer = "m2"
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layer_properties.hierarchical_predecode.vertical_supply = True
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layer_properties.hierarchical_predecode.force_horizontal_input_contact = True
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layer_properties.bank.stack = "m2_stack"
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layer_properties.bank.pitch = "m3_pitch"
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@@ -265,7 +273,7 @@ layer_properties.port_address.supply_offset = True
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layer_properties.port_data.enable_layer = "m1"
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layer_properties.port_data.channel_route_bitlines = False
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layer_properties.replica_column.even_rows = True
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layer_properties.replica_column.even_rows = False
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layer_properties.wordline_driver.vertical_supply = True
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