checkpoint from tt submission

compiler/tests/05_bitcell_array_test.py

@@ -31,7 +31,7 @@ class array_test(openram_test):
             num_spare_rows = 0
             num_spare_cols = 0
 
-        a = factory.create(module_type="bitcell_array", cols=8 + num_spare_cols, rows=8 + num_spare_rows)
+        a = factory.create(module_type="bitcell_array", cols=2 + num_spare_cols, rows=2 + num_spare_rows)
         self.local_check(a)
 
         openram.end_openram()

compiler/tests/14_capped_replica_bitcell_array_norbl_1rw_test.py

@@ -26,7 +26,7 @@ class capped_replica_bitcell_array_norbl_1rw_test(openram_test):
         openram.setup_bitcell()
 
         debug.info(2, "Testing 7x5 capped replica array for 1rw cell without replica column or dummy row")
-        a = factory.create(module_type="capped_replica_bitcell_array", cols=7, rows=5, rbl=[0, 0])
+        a = factory.create(module_type="capped_replica_bitcell_array", cols=8, rows=6, rbl=[0, 0])
         self.local_check(a)
 
         openram.end_openram()

compiler/tests/14_replica_bitcell_array_leftrbl_1rw_test.py

@@ -26,7 +26,7 @@ class replica_bitcell_array_leftrbl_1rw_test(openram_test):
         openram.setup_bitcell()
 
         debug.info(2, "Testing 7x5 replica array for 1rw cell with left replica column")
-        a = factory.create(module_type="replica_bitcell_array", cols=7, rows=5, rbl=[1, 0], left_rbl=[0])
+        a = factory.create(module_type="replica_bitcell_array", cols=8, rows=8, rbl=[1, 0], left_rbl=[0])
         self.local_check(a)
 
         openram.end_openram()

compiler/tests/19_single_bank_2mux_test.py

@@ -24,7 +24,9 @@ class single_bank_test(openram_test):
         from openram import sram_config
 
         c = sram_config(word_size=4,
-                        num_words=16)
+                        num_words=16,
+                        num_spare_cols=1,
+                        num_spare_rows=1)
 
         c.num_words=32
         c.words_per_row=2