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OpenRAM
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updated gitignore and regression make to ignore gf180. Fixed issue with rom decoder routing

This commit is contained in:
SWalker 2023-10-26 21:56:13 -07:00
parent bd9ebc3300
commit 5378a308c1
4 changed files with 18 additions and 5 deletions
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4
.gitignore vendored
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@ -21,6 +21,10 @@ openram.egg-info/
miniconda/ miniconda/
sky130A/ sky130A/
sky130B/ sky130B/
gf180mcuA/
gf180mcuB/
gf180mcuC/
gf180mcuD/
skywater-pdk/ skywater-pdk/
sky130_fd_bd_sram/ sky130_fd_bd_sram/
docker/openram-ubuntu.log docker/openram-ubuntu.log

6
compiler/modules/rom_address_control_buf.py
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@ -119,12 +119,12 @@ class rom_address_control_buf(design):
ppoly_center = poly_right - 0.7 * self.poly_width ppoly_center = poly_right - 0.7 * self.poly_width
poly_y = A_out.cy() poly_y = A_out.cy()
# Placement of gate contacts for NAND cell are different in gf180 which requires tech-specific placement.
if OPTS.tech_name == "gf180mcu": if OPTS.tech_name == "gf180mcu":
poly_y = vdd_rail.cy() + 0.5 * drc("minwidth_tx") * 3 + self.poly_extend_active poly_y = vdd_rail.cy() + 0.5 * drc("minwidth_tx") * 3 + self.poly_extend_active
ppoly_center = A_out.cx() + 0.5 * self.interconnect_width + 0.5 * self.poly_width ppoly_center = A_out.cx() + 0.5 * self.interconnect_width + 0.5 * self.poly_width
else:
ppoly_center = poly_right - 0.7 * self.poly_width
poly_y = A_out.cy()
contact_offset = vector(ppoly_center, clk2_pin.cy()) contact_offset = vector(ppoly_center, clk2_pin.cy())

11
compiler/modules/rom_decoder.py
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@ -18,7 +18,7 @@ class rom_decoder(design):
# array gets rotated 90deg so rows/cols switch # array gets rotated 90deg so rows/cols switch
if "li" in layer: if "li" in layer:
self.output_layer = "m1" self.output_layer = "m1"
self.inv_route_layer = "m2" self.inv_route_layer = "m1"
else: else:
self.output_layer = "m1" self.output_layer = "m1"
self.inv_route_layer = "m3" self.inv_route_layer = "m3"
@ -239,6 +239,15 @@ class rom_decoder(design):
self.add_via_stack_center(offset=addr_bar_pin.center(), self.add_via_stack_center(offset=addr_bar_pin.center(),
from_layer=addr_bar_pin.layer, from_layer=addr_bar_pin.layer,
to_layer=self.inv_route_layer) to_layer=self.inv_route_layer)
self.add_via_stack_center(offset=addr_out_pin.center(),
from_layer=addr_out_pin.layer,
to_layer=self.inv_route_layer)
self.add_via_stack_center(offset=addr_bar_out_pin.center(),
from_layer=addr_bar_out_pin.layer,
to_layer=self.inv_route_layer)
self.copy_layout_pin(self.buf_inst, "A{}_in".format(i), "A{}".format(i)) self.copy_layout_pin(self.buf_inst, "A{}_in".format(i), "A{}".format(i))
def route_supplies(self): def route_supplies(self):

2
compiler/tests/Makefile
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@ -5,7 +5,7 @@ include $(TOP_DIR)/openram.mk
ARGS ?= ARGS ?=
TEST_TECHS ?= scn4m_subm freepdk45 TEST_TECHS ?= scn4m_subm freepdk45
TECHS ?= scn4m_subm freepdk45 sky130 gf180mcu TECHS ?= scn4m_subm freepdk45 sky130
TEST_DIR = $(TOP_DIR)/compiler/tests TEST_DIR = $(TOP_DIR)/compiler/tests
TEST_SRCS = $(sort $(notdir $(wildcard $(TEST_DIR)/*_test.py))) TEST_SRCS = $(sort $(notdir $(wildcard $(TEST_DIR)/*_test.py)))