From 5378a308c1deb4b4b33cfea1b44feab9e218c454 Mon Sep 17 00:00:00 2001
From: SWalker <jswalker@ucsc.edu>
Date: Thu, 26 Oct 2023 21:56:13 -0700
Subject: [PATCH] updated gitignore and regression make to ignore gf180. Fixed
 issue with rom decoder routing

---
 .gitignore                                  |  4 ++++
 compiler/modules/rom_address_control_buf.py |  6 +++---
 compiler/modules/rom_decoder.py             | 11 ++++++++++-
 compiler/tests/Makefile                     |  2 +-
 4 files changed, 18 insertions(+), 5 deletions(-)

diff --git a/.gitignore b/.gitignore
index cb5e29e1..07af627d 100644
--- a/.gitignore
+++ b/.gitignore
@@ -21,6 +21,10 @@ openram.egg-info/
 miniconda/
 sky130A/
 sky130B/
+gf180mcuA/
+gf180mcuB/
+gf180mcuC/
+gf180mcuD/
 skywater-pdk/
 sky130_fd_bd_sram/
 docker/openram-ubuntu.log
diff --git a/compiler/modules/rom_address_control_buf.py b/compiler/modules/rom_address_control_buf.py
index 4a413ce0..d3b1dd47 100644
--- a/compiler/modules/rom_address_control_buf.py
+++ b/compiler/modules/rom_address_control_buf.py
@@ -119,12 +119,12 @@ class rom_address_control_buf(design):
 
         ppoly_center = poly_right - 0.7 * self.poly_width
         poly_y = A_out.cy()
+
+        # Placement of gate contacts for NAND cell are different in gf180 which requires tech-specific placement.
         if OPTS.tech_name == "gf180mcu":
             poly_y = vdd_rail.cy() + 0.5 * drc("minwidth_tx") * 3 + self.poly_extend_active
             ppoly_center = A_out.cx() + 0.5 * self.interconnect_width + 0.5 * self.poly_width
-        else:
-            ppoly_center = poly_right - 0.7 * self.poly_width
-            poly_y = A_out.cy()
+
 
         contact_offset = vector(ppoly_center, clk2_pin.cy())
 
diff --git a/compiler/modules/rom_decoder.py b/compiler/modules/rom_decoder.py
index 8ea798a6..7d6dd928 100644
--- a/compiler/modules/rom_decoder.py
+++ b/compiler/modules/rom_decoder.py
@@ -18,7 +18,7 @@ class rom_decoder(design):
         # array gets rotated 90deg so rows/cols switch
         if "li" in layer:
             self.output_layer = "m1"
-            self.inv_route_layer = "m2"
+            self.inv_route_layer = "m1"
         else:
             self.output_layer = "m1"
             self.inv_route_layer = "m3"
@@ -239,6 +239,15 @@ class rom_decoder(design):
             self.add_via_stack_center(offset=addr_bar_pin.center(),
                                       from_layer=addr_bar_pin.layer,
                                       to_layer=self.inv_route_layer)
+
+            self.add_via_stack_center(offset=addr_out_pin.center(),
+                                      from_layer=addr_out_pin.layer,
+                                      to_layer=self.inv_route_layer)
+
+            self.add_via_stack_center(offset=addr_bar_out_pin.center(),
+                                      from_layer=addr_bar_out_pin.layer,
+                                      to_layer=self.inv_route_layer)
+
             self.copy_layout_pin(self.buf_inst, "A{}_in".format(i), "A{}".format(i))
 
     def route_supplies(self):
diff --git a/compiler/tests/Makefile b/compiler/tests/Makefile
index 5801a850..c4019dbf 100644
--- a/compiler/tests/Makefile
+++ b/compiler/tests/Makefile
@@ -5,7 +5,7 @@ include $(TOP_DIR)/openram.mk
 
 ARGS ?=
 TEST_TECHS ?= scn4m_subm freepdk45
-TECHS ?= scn4m_subm freepdk45 sky130 gf180mcu
+TECHS ?= scn4m_subm freepdk45 sky130
 
 TEST_DIR   = $(TOP_DIR)/compiler/tests
 TEST_SRCS  = $(sort $(notdir $(wildcard $(TEST_DIR)/*_test.py)))