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All bitcells need a vdd/gnd pin

This commit is contained in:
mrg 2020-06-28 15:09:47 -07:00
parent 751eab202b
commit 5285468380
1 changed files with 6 additions and 5 deletions
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5
compiler/modules/bitcell_base_array.py
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@ -102,9 +102,10 @@ class bitcell_base_array(design.design):
width=self.width,
height=wl_pin.height())
# Copy a vdd/gnd layout pin from every column in the first row
# Copy a vdd/gnd layout pin from every cell
for row in range(self.row_size):
for col in range(self.column_size):
inst = self.cell_inst[0, col]
inst = self.cell_inst[row, col]
for pin_name in ["vdd", "gnd"]:
self.copy_layout_pin(inst, pin_name)