From 5285468380cfd20e8dc61f58a6503a883a9c131b Mon Sep 17 00:00:00 2001 From: mrg Date: Sun, 28 Jun 2020 15:09:47 -0700 Subject: [PATCH] All bitcells need a vdd/gnd pin --- compiler/modules/bitcell_base_array.py | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/compiler/modules/bitcell_base_array.py b/compiler/modules/bitcell_base_array.py index e162c225..7d241b4d 100644 --- a/compiler/modules/bitcell_base_array.py +++ b/compiler/modules/bitcell_base_array.py @@ -102,11 +102,12 @@ class bitcell_base_array(design.design): width=self.width, height=wl_pin.height()) - # Copy a vdd/gnd layout pin from every column in the first row - for col in range(self.column_size): - inst = self.cell_inst[0, col] - for pin_name in ["vdd", "gnd"]: - self.copy_layout_pin(inst, pin_name) + # Copy a vdd/gnd layout pin from every cell + for row in range(self.row_size): + for col in range(self.column_size): + inst = self.cell_inst[row, col] + for pin_name in ["vdd", "gnd"]: + self.copy_layout_pin(inst, pin_name) def _adjust_x_offset(self, xoffset, col, col_offset): tempx = xoffset