From 5258016c9f3923eaa9dfcff2d176c21039e0594f Mon Sep 17 00:00:00 2001 From: jsowash Date: Sat, 6 Jul 2019 12:27:24 -0700 Subject: [PATCH] Changed location of port for din_reg. --- compiler/base/verilog.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/base/verilog.py b/compiler/base/verilog.py index 2b6e10ff..c4d4ee00 100644 --- a/compiler/base/verilog.py +++ b/compiler/base/verilog.py @@ -197,7 +197,7 @@ class verilog: self.vf.write(" mem[ADDR{0}_reg][{1}:{2}] = DIN{0}_reg[{1}:{2}];\n".format(port,upper,lower)) self.vf.write(" end\n") else: - self.vf.write(" mem[ADDR{0}_reg] = DIN_reg{0};\n".format(port)) + self.vf.write(" mem[ADDR{0}_reg] = DIN{0}_reg;\n".format(port)) self.vf.write(" end\n") def add_read_block(self, port):