luke/OpenRAM
1
0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 17:39:02 +02:00
Code Issues Packages Projects Releases Wiki Activity

Added option to use delay chain size defined in tech.py

Browse Source
This commit is contained in:
Hunter Nichols
2018-12-14 18:02:19 -08:00
parent dc20bf9e11
commit 51b1bd46da
4 changed files with 40 additions and 15 deletions
Download Patch File Download Diff File Expand all files Collapse all files
compiler/modules/control_logic.py
+32 -15
View File
@@ -109,24 +109,41 @@ class control_logic(design.design):
from importlib import reload
c = reload(__import__(OPTS.replica_bitline))
replica_bitline = getattr(c, OPTS.replica_bitline)
delay_stages_heuristic, delay_fanout_heuristic = self.get_heuristic_delay_chain_size()
bitcell_loads = int(math.ceil(self.num_rows * parameter["rbl_height_percentage"]))
self.replica_bitline = replica_bitline([delay_fanout_heuristic]*delay_stages_heuristic, bitcell_loads, name="replica_bitline_"+self.port_type)
if self.sram != None:
self.set_sen_wl_delays()
if self.sram != None and self.enable_delay_chain_resizing and not self.does_sen_total_timing_match(): #check condition based on resizing method
#This resizes to match fall and rise delays, can make the delay chain weird sizes.
# stage_list = self.get_dynamic_delay_fanout_list(delay_stages_heuristic, delay_fanout_heuristic)
# self.replica_bitline = replica_bitline(stage_list, bitcell_loads, name="replica_bitline_resized_"+self.port_type)
if OPTS.use_tech_delay_chain_size: #Use tech parameters if set.
delay_stages = parameter["static_delay_stages"]
delay_fanout = parameter["static_fanout_per_stage"]
debug.info(1, "Using tech parameters to size delay chain: stages={}, fanout={}".format(delay_stages,delay_fanout))
self.replica_bitline = replica_bitline([delay_fanout]*delay_stages,
bitcell_loads,
name="replica_bitline_"+self.port_type)
#This resizes based on total delay.
delay_stages, delay_fanout = self.get_dynamic_delay_chain_size(delay_stages_heuristic, delay_fanout_heuristic)
self.replica_bitline = replica_bitline([delay_fanout]*delay_stages, bitcell_loads, name="replica_bitline_resized_"+self.port_type)
else: #Otherwise, use a heuristic and/or model based sizing.
#First use a heuristic
delay_stages_heuristic, delay_fanout_heuristic = self.get_heuristic_delay_chain_size()
self.replica_bitline = replica_bitline([delay_fanout_heuristic]*delay_stages_heuristic,
bitcell_loads,
name="replica_bitline_"+self.port_type)
self.sen_delay_rise,self.sen_delay_fall = self.get_delays_to_sen() #get the new timing
#Use a model to determine the delays with that heuristic
if self.sram != None:
self.set_sen_wl_delays()
#Resize if necessary
if self.sram != None and self.enable_delay_chain_resizing and not self.does_sen_total_timing_match(): #check condition based on resizing method
#This resizes to match fall and rise delays, can make the delay chain weird sizes.
# stage_list = self.get_dynamic_delay_fanout_list(delay_stages_heuristic, delay_fanout_heuristic)
# self.replica_bitline = replica_bitline(stage_list,
# bitcell_loads,
# name="replica_bitline_resized_"+self.port_type)
#This resizes based on total delay.
delay_stages, delay_fanout = self.get_dynamic_delay_chain_size(delay_stages_heuristic, delay_fanout_heuristic)
self.replica_bitline = replica_bitline([delay_fanout]*delay_stages,
bitcell_loads,
name="replica_bitline_resized_"+self.port_type)
self.sen_delay_rise,self.sen_delay_fall = self.get_delays_to_sen() #get the new timing
self.add_mod(self.replica_bitline)