luke/OpenRAM
1
0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 17:39:02 +02:00
Code Issues Packages Projects Releases Wiki Activity

fix mirroring of cap cells in cap rows

Browse Source
This commit is contained in:
samuelkcrow
2023-02-14 10:59:00 -08:00
parent 2565305158
commit 51a7161cd7
1 changed files with 2 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files
compiler/modules/capped_replica_bitcell_array.py
+2 -2
View File
@@ -103,7 +103,7 @@ class capped_replica_bitcell_array(bitcell_base_array):
cols=self.column_size + len(self.rbls),
rows=1,
# dummy column + left replica column(s)
column_offset=1 + len(self.left_rbl),
column_offset=1,
mirror=0,
location="top")
@@ -111,7 +111,7 @@ class capped_replica_bitcell_array(bitcell_base_array):
cols=self.column_size + len(self.rbls),
rows=1,
# dummy column + left replica column(s)
column_offset=1 + len(self.left_rbl),
column_offset=1,
mirror=0,
location="bottom")