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OpenRAM
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Fix a couple supply routing issues.

This commit is contained in:
mrg 2022-05-03 11:45:51 -07:00
parent f8f3f16b1f
commit 50045e54e8
5 changed files with 34 additions and 55 deletions
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22
compiler/base/hierarchy_layout.py
View File

@ -657,12 +657,13 @@ class layout():
via_width=None via_width=None
via_height=0 via_height=0
bot_y = min([pin.by() for (inst,pin) in v])
top_y = max([pin.uy() for (inst,pin) in v])
if full_width: if full_width:
bot_y = 0 bot_y = min(0, bot_y)
top_y = self.height top_y = max(self.height, top_y)
else:
bot_y = min([pin.by() for (inst,pin) in v])
top_y = max([pin.uy() for (inst,pin) in v])
top_pos = vector(x, top_y + 0.5 * via_height) top_pos = vector(x, top_y + 0.5 * via_height)
bot_pos = vector(x, bot_y - 0.5 * via_height) bot_pos = vector(x, bot_y - 0.5 * via_height)
@ -758,12 +759,13 @@ class layout():
via_height=None via_height=None
via_width=0 via_width=0
left_x = min([pin.lx() for (inst,pin) in v])
right_x = max([pin.rx() for (inst,pin) in v])
if full_width: if full_width:
left_x = 0 left_x = min(0, left_x)
right_x = self.width right_x = max(self.width, right_x)
else:
left_x = min([pin.lx() for (inst,pin) in v])
right_x = max([pin.rx() for (inst,pin) in v])
left_pos = vector(left_x + 0.5 * via_width, y) left_pos = vector(left_x + 0.5 * via_width, y)
right_pos = vector(right_x + 0.5 * via_width, y) right_pos = vector(right_x + 0.5 * via_width, y)

5
compiler/modules/column_mux_array.py
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@ -147,13 +147,14 @@ class column_mux_array(design.design):
offset=offset, offset=offset,
height=self.height - offset.y) height=self.height - offset.y)
for inst in self.mux_inst: def route_supplies(self):
self.copy_layout_pin(inst, "gnd") self.route_horizontal_pins("gnd", self.insts)
def add_routing(self): def add_routing(self):
self.add_horizontal_input_rail() self.add_horizontal_input_rail()
self.add_vertical_poly_rail() self.add_vertical_poly_rail()
self.route_bitlines() self.route_bitlines()
self.route_supplies()
def add_horizontal_input_rail(self): def add_horizontal_input_rail(self):
""" Create address input rails below the mux transistors """ """ Create address input rails below the mux transistors """

6
compiler/modules/replica_bitcell_array.py
View File

@ -507,12 +507,14 @@ class replica_bitcell_array(bitcell_base_array):
# There are always vertical pins for the WLs on the left/right if we have unused wordlines # There are always vertical pins for the WLs on the left/right if we have unused wordlines
self.left_gnd_locs = self.route_side_pin("gnd", "left", left_right_mult) self.left_gnd_locs = self.route_side_pin("gnd", "left", left_right_mult)
self.right_gnd_locs = self.route_side_pin("gnd","right", left_right_mult) self.right_gnd_locs = self.route_side_pin("gnd","right", left_right_mult)
left_right_mult = 3 # This needs to be big enough so that they aren't in the same supply routing grid
left_right_mult = 4
if gnd_dir == "V": if gnd_dir == "V":
self.top_gnd_locs = self.route_side_pin("gnd", "top", top_bot_mult) self.top_gnd_locs = self.route_side_pin("gnd", "top", top_bot_mult)
self.bot_gnd_locs = self.route_side_pin("gnd", "bot", top_bot_mult) self.bot_gnd_locs = self.route_side_pin("gnd", "bot", top_bot_mult)
top_bot_mult = 3 # This needs to be big enough so that they aren't in the same supply routing grid
top_bot_mult = 4
if vdd_dir == "V": if vdd_dir == "V":
self.top_vdd_locs = self.route_side_pin("vdd", "top", top_bot_mult) self.top_vdd_locs = self.route_side_pin("vdd", "top", top_bot_mult)

7
compiler/pgates/column_mux.py
View File

@ -240,10 +240,9 @@ class column_mux(pgate.pgate):
self.add_via_center(layers=self.col_mux_stack, self.add_via_center(layers=self.col_mux_stack,
offset=active_pos) offset=active_pos)
# Add the M1->..->power_grid_layer stack self.add_layout_pin_rect_center(text="gnd",
self.add_power_pin(name="gnd", layer="m1",
loc=active_pos, offset=active_pos)
start_layer="m1")
# Add well enclosure over all the tx and contact # Add well enclosure over all the tx and contact
if "pwell" in layer: if "pwell" in layer:

49
compiler/pgates/precharge.py
View File

@ -96,46 +96,21 @@ class precharge(design.design):
Adds a vdd rail at the top of the cell Adds a vdd rail at the top of the cell
""" """
if OPTS.experimental_power: pmos_pin = self.upper_pmos2_inst.get_pin("S")
pmos_pin = self.upper_pmos2_inst.get_pin("S") pmos_pos = pmos_pin.center()
pmos_pos = pmos_pin.center() self.add_path(pmos_pin.layer, [pmos_pos, self.well_contact_pos])
self.add_path(pmos_pin.layer, [pmos_pos, self.well_contact_pos])
self.add_via_stack_center(from_layer=pmos_pin.layer, self.add_via_stack_center(from_layer=pmos_pin.layer,
to_layer=self.supply_stack[0], to_layer=self.supply_stack[0],
offset=self.well_contact_pos)
self.add_min_area_rect_center(layer=self.en_layer,
offset=self.well_contact_pos, offset=self.well_contact_pos,
directions=("V", "V")) width=self.well_contact.mod.second_layer_width)
self.add_min_area_rect_center(layer=self.en_layer, self.add_layout_pin_rect_center(text="vdd",
offset=self.well_contact_pos, layer=self.supply_stack[0],
width=self.well_contact.mod.second_layer_width) offset=self.well_contact_pos)
self.add_layout_pin_rect_center(text="vdd",
layer=self.supply_stack[0],
offset=self.well_contact_pos)
else:
# Adds the rail across the width of the cell
vdd_position = vector(0.5 * self.width, self.height)
layer_width = drc("minwidth_" + self.en_layer)
self.add_rect_center(layer=self.en_layer,
offset=vdd_position,
width=self.width,
height=layer_width)
pmos_pin = self.upper_pmos2_inst.get_pin("S")
# center of vdd rail
pmos_vdd_pos = vector(pmos_pin.cx(), vdd_position.y)
self.add_path(self.en_layer, [pmos_pin.center(), pmos_vdd_pos])
self.add_power_pin("vdd",
self.well_contact_pos,
directions=("V", "V"))
self.add_via_stack_center(from_layer=pmos_pin.layer,
to_layer=self.en_layer,
offset=pmos_pin.center(),
directions=("V", "V"))
def create_ptx(self): def create_ptx(self):
""" """