Fix a couple supply routing issues.

compiler/modules/column_mux_array.py

@@ -147,13 +147,14 @@ class column_mux_array(design.design):
                                 offset=offset,
                                 height=self.height - offset.y)
 
-        for inst in self.mux_inst:
-            self.copy_layout_pin(inst, "gnd")
+    def route_supplies(self):
+        self.route_horizontal_pins("gnd", self.insts)
 
     def add_routing(self):
         self.add_horizontal_input_rail()
         self.add_vertical_poly_rail()
         self.route_bitlines()
+        self.route_supplies()
 
     def add_horizontal_input_rail(self):
         """ Create address input rails below the mux transistors  """

compiler/modules/replica_bitcell_array.py

@@ -507,12 +507,14 @@ class replica_bitcell_array(bitcell_base_array):
         # There are always vertical pins for the WLs on the left/right if we have unused wordlines
         self.left_gnd_locs = self.route_side_pin("gnd", "left", left_right_mult)
         self.right_gnd_locs = self.route_side_pin("gnd","right", left_right_mult)
-        left_right_mult = 3
+        # This needs to be big enough so that they aren't in the same supply routing grid
+        left_right_mult = 4
 
         if gnd_dir == "V":
             self.top_gnd_locs = self.route_side_pin("gnd", "top", top_bot_mult)
             self.bot_gnd_locs = self.route_side_pin("gnd", "bot", top_bot_mult)
-            top_bot_mult = 3
+            # This needs to be big enough so that they aren't in the same supply routing grid
+            top_bot_mult = 4
 
         if vdd_dir == "V":
             self.top_vdd_locs = self.route_side_pin("vdd", "top", top_bot_mult)