From 4fa084f2720302756b81a663926d902fbb8fe2da Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 17 Dec 2021 10:18:20 -0800 Subject: [PATCH] Add 1rw decoder test --- compiler/tests/04_and2_dec_test.py | 11 ++++++++++- compiler/tests/04_and3_dec_test.py | 12 +++++++++++- compiler/tests/04_and4_dec_test.py | 11 ++++++++++- 3 files changed, 31 insertions(+), 3 deletions(-) diff --git a/compiler/tests/04_and2_dec_test.py b/compiler/tests/04_and2_dec_test.py index 009a04f1..69bdd676 100755 --- a/compiler/tests/04_and2_dec_test.py +++ b/compiler/tests/04_and2_dec_test.py @@ -29,7 +29,16 @@ class and2_dec_test(openram_test): OPTS.num_w_ports = 0 globals.setup_bitcell() - debug.info(2, "Testing and2_dec gate") + debug.info(2, "Testing and2_dec 1rw/1r gate") + a = factory.create(module_type="and2_dec") + self.local_check(a) + + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 0 + OPTS.num_w_ports = 0 + globals.setup_bitcell() + + debug.info(2, "Testing and2_dec 1rw gate") a = factory.create(module_type="and2_dec") self.local_check(a) diff --git a/compiler/tests/04_and3_dec_test.py b/compiler/tests/04_and3_dec_test.py index a7cb6ef1..bcf4e85b 100755 --- a/compiler/tests/04_and3_dec_test.py +++ b/compiler/tests/04_and3_dec_test.py @@ -15,6 +15,7 @@ from globals import OPTS from sram_factory import factory import debug + class and3_dec_test(openram_test): def runTest(self): @@ -28,7 +29,16 @@ class and3_dec_test(openram_test): OPTS.num_w_ports = 0 globals.setup_bitcell() - debug.info(2, "Testing and3_dec gate") + debug.info(2, "Testing and3_dec 1rw/1r gate") + a = factory.create(module_type="and3_dec") + self.local_check(a) + + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 0 + OPTS.num_w_ports = 0 + globals.setup_bitcell() + + debug.info(2, "Testing and3_dec 1rw gate") a = factory.create(module_type="and3_dec") self.local_check(a) diff --git a/compiler/tests/04_and4_dec_test.py b/compiler/tests/04_and4_dec_test.py index ec76435f..4dbb2613 100755 --- a/compiler/tests/04_and4_dec_test.py +++ b/compiler/tests/04_and4_dec_test.py @@ -30,7 +30,16 @@ class and4_dec_test(openram_test): OPTS.num_w_ports = 0 globals.setup_bitcell() - debug.info(2, "Testing and4_dec gate") + debug.info(2, "Testing and4_dec 1rw/1r gate") + a = factory.create(module_type="and4_dec") + self.local_check(a) + + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 0 + OPTS.num_w_ports = 0 + globals.setup_bitcell() + + debug.info(2, "Testing and4_dec 1rw gate") a = factory.create(module_type="and4_dec") self.local_check(a)