Added custom 1rw+1r bitcell. Testing are currently failing.

compiler/base/utils.py

@@ -3,6 +3,7 @@ import gdsMill
 import tech
 import math
 import globals
+import debug
 from vector import vector
 from pin_layout import pin_layout
 
@@ -65,6 +66,7 @@ def get_gds_size(name, gds_filename, units, layer):
     Open a GDS file and return the size from either the
     bounding box or a border layer.
     """
+    debug.info(2,"Creating VLSI layout for {}".format(name))
     cell_vlsi = gdsMill.VlsiLayout(units=units)
     reader = gdsMill.Gds2reader(cell_vlsi)
     reader.loadFromFile(gds_filename)
@@ -72,6 +74,7 @@ def get_gds_size(name, gds_filename, units, layer):
     cell = {}
     measure_result = cell_vlsi.getLayoutBorder(layer)
     if measure_result == None:
+        debug.info(2,"Layout border failed. Trying to measure size for {}".format(name))
         measure_result = cell_vlsi.measureSize(name)
     # returns width,height
     return measure_result

compiler/example_config_scn4m_subm.py

@@ -11,9 +11,9 @@ output_path = "temp"
 output_name = "sram_{0}_{1}_{2}_{3}".format(word_size,num_words,num_banks,tech_name)
 
 #Setting for multiport
-netlist_only = True
-bitcell = "pbitcell"
-replica_bitcell="replica_pbitcell"
-num_rw_ports = 1
-num_r_ports = 1
-num_w_ports = 0
+# netlist_only = True
+# bitcell = "pbitcell"
+# replica_bitcell="replica_pbitcell"
+# num_rw_ports = 1
+# num_r_ports = 1
+# num_w_ports = 0

compiler/gdsMill/gdsMill/vlsiLayout.py

@@ -155,10 +155,10 @@ class VlsiLayout:
     def traverseTheHierarchy(self, startingStructureName=None, delegateFunction = None, 
                              transformPath = [], rotateAngle = 0, transFlags = [0,0,0], coordinates = (0,0)):
         #since this is a recursive function, must deal with the default
-        #parameters explicitly        
+        #parameters explicitly      
         if startingStructureName == None:
             startingStructureName = self.rootStructureName            
-
+            
         #set up the rotation matrix        
         if(rotateAngle == None or rotateAngle == ""):
             angle = 0

compiler/modules/bitcell_1rw_1r.py

@@ -0,0 +1,98 @@
+import design
+import debug
+import utils
+from tech import GDS,layer
+
+class bitcell_1rw_1r(design.design):
+    """
+    A single bit cell (6T, 8T, etc.)  This module implements the
+    single memory cell used in the design. It is a hand-made cell, so
+    the layout and netlist should be available in the technology
+    library.
+    """
+
+    pin_names = ["bl0", "br0", "bl1", "br1", "wl0", "wl1", "vdd", "gnd"]
+    (width,height) = utils.get_libcell_size("cell_1rw_1r", GDS["unit"], layer["boundary"])
+    pin_map = utils.get_libcell_pins(pin_names, "cell_1rw_1r", GDS["unit"], layer["boundary"])
+
+    def __init__(self):
+        design.design.__init__(self, "cell_1rw_1r")
+        debug.info(2, "Create bitcell with 1RW and 1R Port")
+
+        self.width = bitcell.width
+        self.height = bitcell.height
+        self.pin_map = bitcell.pin_map
+
+    def analytical_delay(self, slew, load=0, swing = 0.5):
+        # delay of bit cell is not like a driver(from WL)
+        # so the slew used should be 0
+        # it should not be slew dependent?
+        # because the value is there
+        # the delay is only over half transsmission gate
+        from tech import spice
+        r = spice["min_tx_r"]*3
+        c_para = spice["min_tx_drain_c"]
+        result = self.cal_delay_with_rc(r = r, c =  c_para+load, slew = slew, swing = swing)
+        return result
+   
+ 
+    def list_bitcell_pins(self, col, row):
+        """ Creates a list of connections in the bitcell, indexed by column and row, for instance use in bitcell_array """
+        bitcell_pins = ["bl0[{0}]".format(col),
+                        "br0[{0}]".format(col),
+                        "bl1[{0}]".format(col),
+                        "br1[{0}]".format(col),
+                        "wl0[{0}]".format(row),
+                        "wl1[{0}]".format(row),
+                        "vdd",
+                        "gnd"]
+        return bitcell_pins
+    
+    def list_all_wl_names(self):
+        """ Creates a list of all wordline pin names """
+        row_pins = ["wl0", "wl1"]    
+        return row_pins
+    
+    def list_all_bitline_names(self):
+        """ Creates a list of all bitline pin names (both bl and br) """
+        column_pins = ["bl0", "br0", "bl1", "br1"]
+        return column_pins
+    
+    def list_all_bl_names(self):
+        """ Creates a list of all bl pins names """
+        column_pins = ["bl0", "bl1"]
+        return column_pins
+        
+    def list_all_br_names(self):
+        """ Creates a list of all br pins names """
+        column_pins = ["br0", "br1"]
+        return column_pins
+        
+    def list_read_bl_names(self):
+        """ Creates a list of bl pin names associated with read ports """
+        column_pins = ["bl0", "bl1"]
+        return column_pins
+    
+    def list_read_br_names(self):
+        """ Creates a list of br pin names associated with read ports """
+        column_pins = ["br0", "br1"]
+        return column_pins
+        
+    def list_write_bl_names(self):
+        """ Creates a list of bl pin names associated with write ports """
+        column_pins = ["bl0"]
+        return column_pins
+    
+    def list_write_br_names(self):
+        """ Creates a list of br pin names asscociated with write ports"""
+        column_pins = ["br0"]
+        return column_pins
+    
+    def analytical_power(self, proc, vdd, temp, load):
+        """Bitcell power in nW. Only characterizes leakage."""
+        from tech import spice
+        leakage = spice["bitcell_leakage"]
+        dynamic = 0 #temporary
+        total_power = self.return_power(dynamic, leakage)
+        return total_power
+

compiler/sram_config.py

@@ -53,7 +53,7 @@ class sram_config:
             # Estimate the number of rows given the tentative words per row
             self.tentative_num_rows = self.num_bits_per_bank / (self.words_per_row*self.word_size)
             self.words_per_row = self.amend_words_per_row(self.tentative_num_rows, self.words_per_row)
-        
+
         # Fix the number of columns and rows
         self.num_cols = int(self.words_per_row*self.word_size)
         self.num_rows = int(self.num_words_per_bank/self.words_per_row)

compiler/tests/04_bitcell_1rw_1r_test.py

@@ -0,0 +1,42 @@
+#!/usr/bin/env python3
+"""
+Run regresion tests on a parameterized bitcell
+"""
+
+import unittest
+from testutils import header,openram_test
+import sys,os
+sys.path.append(os.path.join(sys.path[0],".."))
+import globals
+from globals import OPTS
+import debug
+
+OPTS = globals.OPTS
+
+#@unittest.skip("SKIPPING 04_bitcell_1rw_1r_test")
+class bitcell_1rw_1r_test(openram_test):
+
+    def runTest(self):
+        OPTS.bitcell = "bitcell_1rw_1r"
+        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        from bitcell import bitcell
+        from bitcell_1rw_1r import bitcell_1rw_1r
+        import tech
+        OPTS.num_rw_ports=1
+        OPTS.num_w_ports=0
+        OPTS.num_r_ports=1
+        debug.info(2, "Bitcell with 1 read/write and 1 read port")
+        #tx = bitcell_1rw_1r()
+        tx = bitcell()
+        self.local_check(tx)
+
+        globals.end_openram()
+
+
+
+# instantiate a copy of the class to actually run the test
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main()