mirror of https://github.com/VLSIDA/OpenRAM.git
added contact to locali for wmask
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parent
22c821f5d8
commit
4e83e8c648
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@ -10,7 +10,7 @@ import debug
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from sram_factory import factory
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from sram_factory import factory
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from vector import vector
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from vector import vector
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from globals import OPTS
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from globals import OPTS
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from tech import layer
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class write_mask_and_array(design.design):
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class write_mask_and_array(design.design):
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"""
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"""
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@ -121,7 +121,10 @@ class write_mask_and_array(design.design):
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for supply in ["gnd", "vdd"]:
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for supply in ["gnd", "vdd"]:
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supply_pin=self.and2_insts[i].get_pin(supply)
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supply_pin=self.and2_insts[i].get_pin(supply)
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self.add_power_pin(supply, supply_pin.center())
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if "li" in layer:
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self.add_power_pin(supply, supply_pin.center(), start_layer="li", directions = ("H", "H"))
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else:
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self.add_power_pin(supply, supply_pin.center())
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for supply in ["gnd", "vdd"]:
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for supply in ["gnd", "vdd"]:
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supply_pin_left = self.and2_insts[0].get_pin(supply)
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supply_pin_left = self.and2_insts[0].get_pin(supply)
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@ -132,5 +135,3 @@ class write_mask_and_array(design.design):
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"""Get the relative capacitance of all the input connections in the bank"""
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"""Get the relative capacitance of all the input connections in the bank"""
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# The enable is connected to an and2 for every row.
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# The enable is connected to an and2 for every row.
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return self.and2.get_cin() * len(self.and2_insts)
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return self.and2.get_cin() * len(self.and2_insts)
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