mirror of https://github.com/VLSIDA/OpenRAM.git
Skip test in sky130
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@ -28,9 +28,11 @@ class replica_bitcell_array_1rw_1r_test(openram_test):
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a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, left_rbl=1, right_rbl=1, bitcell_ports=[0, 1])
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a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, left_rbl=1, right_rbl=1, bitcell_ports=[0, 1])
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self.local_check(a)
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self.local_check(a)
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debug.info(2, "Testing 4x4 array for cell_1rw_1r")
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# Sky 130 has restrictions on the symmetries
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a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, left_rbl=2, right_rbl=0, bitcell_ports=[0, 1])
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if OPTS.tech_name != "sky130":
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self.local_check(a)
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debug.info(2, "Testing 4x4 array for cell_1rw_1r")
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a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, left_rbl=2, right_rbl=0, bitcell_ports=[0, 1])
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self.local_check(a)
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globals.end_openram()
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globals.end_openram()
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