diff --git a/compiler/tests/14_replica_bitcell_array_1rw_1r_test.py b/compiler/tests/14_replica_bitcell_array_1rw_1r_test.py
index a36fc80f..626725c4 100755
--- a/compiler/tests/14_replica_bitcell_array_1rw_1r_test.py
+++ b/compiler/tests/14_replica_bitcell_array_1rw_1r_test.py
@@ -28,9 +28,11 @@ class replica_bitcell_array_1rw_1r_test(openram_test):
         a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, left_rbl=1, right_rbl=1, bitcell_ports=[0, 1])
         self.local_check(a)
 
-        debug.info(2, "Testing 4x4 array for cell_1rw_1r")
-        a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, left_rbl=2, right_rbl=0, bitcell_ports=[0, 1])
-        self.local_check(a)
+        # Sky 130 has restrictions on the symmetries
+        if OPTS.tech_name != "sky130":
+            debug.info(2, "Testing 4x4 array for cell_1rw_1r")
+            a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, left_rbl=2, right_rbl=0, bitcell_ports=[0, 1])
+            self.local_check(a)
 
         globals.end_openram()