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OpenRAM
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Check min size inverter.

This commit is contained in:
mrg 2020-05-13 16:54:26 -07:00
parent f8bcc54338
commit 4b526f0d5f
2 changed files with 2 additions and 1 deletions
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2
compiler/modules/write_mask_and_array.py
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@ -60,7 +60,7 @@ class write_mask_and_array(design.design):
# Size the AND gate for the number of write drivers it drives, which is equal to the write size. # Size the AND gate for the number of write drivers it drives, which is equal to the write size.
# Assume stage effort of 3 to compute the size # Assume stage effort of 3 to compute the size
self.and2 = factory.create(module_type="pand2", self.and2 = factory.create(module_type="pand2",
size=self.write_size / 4.0) size=max(self.write_size / 4.0, 1))
self.add_mod(self.and2) self.add_mod(self.and2)
def create_and2_array(self): def create_and2_array(self):

1
compiler/pgates/pinv.py
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@ -40,6 +40,7 @@ class pinv(pgate.pgate):
self.add_comment("size: {}".format(size)) self.add_comment("size: {}".format(size))
self.size = size self.size = size
debug.check(self.size >= 1, "Must have a size greater than or equal to 1.")
self.nmos_size = size self.nmos_size = size
self.pmos_size = beta * size self.pmos_size = beta * size
self.beta = beta self.beta = beta