From 4b526f0d5fd970a87628aadf85183045ab06cbe0 Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 13 May 2020 16:54:26 -0700 Subject: [PATCH] Check min size inverter. --- compiler/modules/write_mask_and_array.py | 2 +- compiler/pgates/pinv.py | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/compiler/modules/write_mask_and_array.py b/compiler/modules/write_mask_and_array.py index 4d4e0c50..e660d519 100644 --- a/compiler/modules/write_mask_and_array.py +++ b/compiler/modules/write_mask_and_array.py @@ -60,7 +60,7 @@ class write_mask_and_array(design.design): # Size the AND gate for the number of write drivers it drives, which is equal to the write size. # Assume stage effort of 3 to compute the size self.and2 = factory.create(module_type="pand2", - size=self.write_size / 4.0) + size=max(self.write_size / 4.0, 1)) self.add_mod(self.and2) def create_and2_array(self): diff --git a/compiler/pgates/pinv.py b/compiler/pgates/pinv.py index 465f7a58..5e1aab7b 100644 --- a/compiler/pgates/pinv.py +++ b/compiler/pgates/pinv.py @@ -40,6 +40,7 @@ class pinv(pgate.pgate): self.add_comment("size: {}".format(size)) self.size = size + debug.check(self.size >= 1, "Must have a size greater than or equal to 1.") self.nmos_size = size self.pmos_size = beta * size self.beta = beta