Check min size inverter.

2026-08-30 01:48:33 +02:00 · 2020-05-13 16:54:26 -07:00
parent f8bcc54338
commit 4b526f0d5f
2 changed files with 2 additions and 1 deletions
@@ -60,7 +60,7 @@ class write_mask_and_array(design.design):
        # Size the AND gate for the number of write drivers it drives, which is equal to the write size.
        # Assume stage effort of 3 to compute the size
        self.and2 = factory.create(module_type="pand2",
-                                   size=self.write_size / 4.0)
+                                   size=max(self.write_size / 4.0, 1))
        self.add_mod(self.and2)

    def create_and2_array(self):