mirror of https://github.com/VLSIDA/OpenRAM.git
parent
5e514215d5
commit
4b06ab9eaf
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@ -224,11 +224,11 @@ class pnand2(pgate.pgate):
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# Non-preferred active contacts
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# Non-preferred active contacts
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self.add_via_center(layers=self.m1_stack,
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self.add_via_center(layers=self.m1_stack,
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directions=("V","H"),
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directions=("V", "H"),
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offset=pmos_pin.center())
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offset=pmos_pin.center())
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# Non-preferred active contacts
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# Non-preferred active contacts
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self.add_via_center(layers=self.m1_stack,
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self.add_via_center(layers=self.m1_stack,
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directions=("V","H"),
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directions=("V", "H"),
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offset=nmos_pin.center())
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offset=nmos_pin.center())
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self.add_via_center(layers=self.m1_stack,
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self.add_via_center(layers=self.m1_stack,
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offset=out_offset)
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offset=out_offset)
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@ -5,21 +5,10 @@
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# (acting for and on behalf of Oklahoma State University)
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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# All rights reserved.
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#
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#
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import sys
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from tech import drc, spice
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import debug
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import debug
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from math import log,sqrt,ceil
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import datetime
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import getpass
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import numpy as np
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from vector import vector
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from vector import vector
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from globals import OPTS, print_time
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from sram_base import sram_base
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from sram_base import sram_base
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from bank import bank
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from contact import m2_via
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from contact import m2_via
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from dff_buf_array import dff_buf_array
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from dff_array import dff_array
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class sram_1bank(sram_base):
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class sram_1bank(sram_base):
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@ -328,10 +317,10 @@ class sram_1bank(sram_base):
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offset=flop_pos)
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offset=flop_pos)
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def route_col_addr_dff(self):
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def route_col_addr_dff(self):
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""" Connect the output of the row flops to the bank pins """
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""" Connect the output of the col flops to the bank pins """
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for port in self.all_ports:
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for port in self.all_ports:
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if port%2:
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if port%2:
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offset = self.col_addr_dff_insts[port].ll() - vector(0, (self.word_size+2)*self.m1_pitch)
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offset = self.col_addr_dff_insts[port].ll() - vector(0, (self.word_size+4)*self.m1_pitch)
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else:
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else:
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offset = self.col_addr_dff_insts[port].ul() + vector(0, 2*self.m1_pitch)
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offset = self.col_addr_dff_insts[port].ul() + vector(0, 2*self.m1_pitch)
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