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Remove OEB signal since we split DIN/DOUT ports

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Matt Guthaus
2018-08-13 14:09:49 -07:00
parent 9ffba4b052
commit 49bee6a96e
5 changed files with 22 additions and 29 deletions
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compiler/characterizer/delay.py
-6
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@@ -166,7 +166,6 @@ class delay():
self.sf.write("\n* Generation of control signals\n")
self.stim.gen_constant(sig_name="CSb", v_val=self.vdd_voltage)
self.stim.gen_constant(sig_name="WEb", v_val=self.vdd_voltage)
self.stim.gen_constant(sig_name="OEb", v_val=self.vdd_voltage)
self.sf.write("\n* Generation of global clock signal\n")
self.stim.gen_constant(sig_name="CLK", v_val=0)
@@ -621,7 +620,6 @@ class delay():
self.cycle_times.append(self.t_current)
self.t_current += self.period
self.web_values.append(1)
self.oeb_values.append(1)
self.csb_values.append(1)
self.add_data(data)
@@ -637,7 +635,6 @@ class delay():
self.t_current += self.period
self.web_values.append(1)
self.oeb_values.append(0)
self.csb_values.append(0)
self.add_data(data)
@@ -654,7 +651,6 @@ class delay():
self.t_current += self.period
self.web_values.append(0)
self.oeb_values.append(1)
self.csb_values.append(0)
self.add_data(data)
@@ -674,7 +670,6 @@ class delay():
# Control logic signals each cycle
self.web_values = []
self.oeb_values = []
self.csb_values = []
# Address and data values for each address/data bit
@@ -798,4 +793,3 @@ class delay():
""" Generates the control signals """
self.stim.gen_pwl("csb", self.cycle_times, self.csb_values, self.period, self.slew, 0.05)
self.stim.gen_pwl("web", self.cycle_times, self.web_values, self.period, self.slew, 0.05)
self.stim.gen_pwl("oeb", self.cycle_times, self.oeb_values, self.period, self.slew, 0.05)