diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py index 2c639ee9..55a3bc06 100644 --- a/compiler/characterizer/delay.py +++ b/compiler/characterizer/delay.py @@ -166,7 +166,6 @@ class delay(): self.sf.write("\n* Generation of control signals\n") self.stim.gen_constant(sig_name="CSb", v_val=self.vdd_voltage) self.stim.gen_constant(sig_name="WEb", v_val=self.vdd_voltage) - self.stim.gen_constant(sig_name="OEb", v_val=self.vdd_voltage) self.sf.write("\n* Generation of global clock signal\n") self.stim.gen_constant(sig_name="CLK", v_val=0) @@ -621,7 +620,6 @@ class delay(): self.cycle_times.append(self.t_current) self.t_current += self.period self.web_values.append(1) - self.oeb_values.append(1) self.csb_values.append(1) self.add_data(data) @@ -637,7 +635,6 @@ class delay(): self.t_current += self.period self.web_values.append(1) - self.oeb_values.append(0) self.csb_values.append(0) self.add_data(data) @@ -654,7 +651,6 @@ class delay(): self.t_current += self.period self.web_values.append(0) - self.oeb_values.append(1) self.csb_values.append(0) self.add_data(data) @@ -674,7 +670,6 @@ class delay(): # Control logic signals each cycle self.web_values = [] - self.oeb_values = [] self.csb_values = [] # Address and data values for each address/data bit @@ -798,4 +793,3 @@ class delay(): """ Generates the control signals """ self.stim.gen_pwl("csb", self.cycle_times, self.csb_values, self.period, self.slew, 0.05) self.stim.gen_pwl("web", self.cycle_times, self.web_values, self.period, self.slew, 0.05) - self.stim.gen_pwl("oeb", self.cycle_times, self.oeb_values, self.period, self.slew, 0.05) diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index 99018a9a..d9f12589 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -52,7 +52,7 @@ class control_logic(design.design): dff = dff_inv() dff_height = dff.height - self.ctrl_dff_array = dff_inv_array(rows=3,columns=1) + self.ctrl_dff_array = dff_inv_array(rows=2,columns=1) self.add_mod(self.ctrl_dff_array) self.nand2 = pnand2(height=dff_height) @@ -93,10 +93,10 @@ class control_logic(design.design): #self.cell_gap = max(self.m2_pitch,drc["pwell_to_nwell"]) # List of input control signals - self.input_list =["csb","web","oeb"] - self.dff_output_list =["cs_bar", "cs", "we_bar", "we", "oe_bar", "oe"] + self.input_list =["csb","web"] + self.dff_output_list =["cs_bar", "cs", "we_bar", "we"] # list of output control signals (for making a vertical bus) - self.internal_bus_list = ["clk_buf", "clk_buf_bar", "we", "cs", "oe"] + self.internal_bus_list = ["clk_buf", "clk_buf_bar", "we", "cs"] # leave space for the bus plus one extra space self.internal_bus_width = (len(self.internal_bus_list)+1)*self.m2_pitch # Ooutputs to the bank @@ -190,14 +190,14 @@ class control_logic(design.design): (y_off,mirror)=self.get_offset(row) - # input: OE, clk_buf_bar,CS output: rbl_in_bar + # input: clk_buf_bar,CS output: rbl_in_bar self.rbl_in_bar_offset = vector(x_off, y_off) self.rbl_in_bar_inst=self.add_inst(name="nand3_rbl_in_bar", - mod=self.nand3, + mod=self.nand2, offset=self.rbl_in_bar_offset, mirror=mirror) - self.connect_inst(["clk_buf_bar", "oe", "cs", "rbl_in_bar", "vdd", "gnd"]) - x_off += self.nand3.width + self.connect_inst(["clk_buf_bar", "cs", "rbl_in_bar", "vdd", "gnd"]) + x_off += self.nand2.width # input: rbl_in_bar, output: rbl_in self.rbl_in_offset = vector(x_off, y_off) @@ -306,7 +306,7 @@ class control_logic(design.design): def route_dffs(self): """ Route the input inverters """ - dff_out_map = zip(["dout_bar[{}]".format(i) for i in range(3)], ["cs", "we", "oe"]) + dff_out_map = zip(["dout_bar[{}]".format(i) for i in range(3)], ["cs", "we"]) self.connect_vertical_bus(dff_out_map, self.ctrl_dff_inst, self.rail_offsets) # Connect the clock rail to the other clock rail @@ -320,7 +320,6 @@ class control_logic(design.design): self.copy_layout_pin(self.ctrl_dff_inst, "din[0]", "csb") self.copy_layout_pin(self.ctrl_dff_inst, "din[1]", "web") - self.copy_layout_pin(self.ctrl_dff_inst, "din[2]", "oeb") def add_dffs(self): @@ -388,7 +387,7 @@ class control_logic(design.design): def route_rbl_in(self): """ Connect the logic for the rbl_in generation """ - rbl_in_map = zip(["A", "B", "C"], ["clk_buf_bar", "oe", "cs"]) + rbl_in_map = zip(["A", "B"], ["clk_buf_bar", "cs"]) self.connect_vertical_bus(rbl_in_map, self.rbl_in_bar_inst, self.rail_offsets) # Connect the NAND3 output to the inverter diff --git a/compiler/tests/21_ngspice_delay_test.py b/compiler/tests/21_ngspice_delay_test.py index 72bdbc65..33fb0e9c 100755 --- a/compiler/tests/21_ngspice_delay_test.py +++ b/compiler/tests/21_ngspice_delay_test.py @@ -61,16 +61,16 @@ class timing_sram_test(openram_test): 'write0_power': [0.04765188], 'write1_power': [0.04434999]} elif OPTS.tech_name == "scn3me_subm": - golden_data = {'delay_hl': [11.69536], - 'delay_lh': [1.260921], - 'leakage_power': 0.00039469710000000004, - 'min_period': 20.0, - 'read0_power': [4.40238], - 'read1_power': [4.126633], - 'slew_hl': [1.259555], - 'slew_lh': [0.9150649], - 'write0_power': [4.988347], - 'write1_power': [4.473887]} + golden_data = {'delay_hl': [3.8551919999999997], + 'delay_lh': [2.649183], + 'leakage_power': 0.001692146, + 'min_period': 4.688, + 'read0_power': [17.34118], + 'read1_power': [16.63607], + 'slew_hl': [1.257066], + 'slew_lh': [1.211681], + 'write0_power': [21.73913], + 'write1_power': [18.39621]} else: self.assertTrue(False) # other techs fail diff --git a/technology/freepdk45/tech/tech.py b/technology/freepdk45/tech/tech.py index 98e0fab3..f232a2a7 100644 --- a/technology/freepdk45/tech/tech.py +++ b/technology/freepdk45/tech/tech.py @@ -261,7 +261,7 @@ spice["nom_temperature"] = 25 # Nominal temperature (celcius) #FIXME: We don't use these everywhere... spice["vdd_name"] = "vdd" spice["gnd_name"] = "gnd" -spice["control_signals"] = ["CSb", "WEb", "OEb"] +spice["control_signals"] = ["CSB", "WEB"] spice["data_name"] = "DATA" spice["addr_name"] = "ADDR" spice["minwidth_tx"] = drc["minwidth_tx"] diff --git a/technology/scn3me_subm/tech/tech.py b/technology/scn3me_subm/tech/tech.py index 0bba8754..18ec5bca 100755 --- a/technology/scn3me_subm/tech/tech.py +++ b/technology/scn3me_subm/tech/tech.py @@ -224,7 +224,7 @@ spice["nom_temperature"] = 25 # Nominal temperature (celcius) #FIXME: We don't use these everywhere... spice["vdd_name"] = "vdd" spice["gnd_name"] = "gnd" -spice["control_signals"] = ["CSb", "WEb", "OEb"] +spice["control_signals"] = ["CSB", "WEB"] spice["data_name"] = "DATA" spice["addr_name"] = "ADDR" spice["minwidth_tx"] = drc["minwidth_tx"]