mirror of https://github.com/VLSIDA/OpenRAM.git
Moved output of tests 23-25 to openram_temp
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7fcce2633f
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@ -32,13 +32,11 @@ class lib_test(unittest.TestCase):
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name="sram_2_16_1_{0}".format(OPTS.tech_name))
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name="sram_2_16_1_{0}".format(OPTS.tech_name))
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OPTS.check_lvsdrc = True
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OPTS.check_lvsdrc = True
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tempspice = OPTS.openram_temp + "temp.sp"
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tempspice = OPTS.openram_temp + "temp.sp"
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s.sp_write(tempspice)
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s.sp_write(tempspice)
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curpath=os.path.dirname(os.path.realpath(__file__)) + "/"
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filename = s.name + ".lib"
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filename = s.name + ".lib"
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libname = curpath + filename
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libname = OPTS.openram_temp + filename
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lib.lib(libname,s,tempspice)
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lib.lib(libname,s,tempspice)
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# let's diff the result with a golden model
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# let's diff the result with a golden model
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@ -32,11 +32,10 @@ class lef_test(unittest.TestCase):
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OPTS.check_lvsdrc = True
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OPTS.check_lvsdrc = True
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curpath=os.path.dirname(os.path.realpath(__file__)) + "/"
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gdsfile = s.name + ".gds"
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gdsfile = s.name + ".gds"
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leffile = s.name + ".lef"
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leffile = s.name + ".lef"
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gdsname = curpath + gdsfile
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gdsname = OPTS.openram_temp + gdsfile
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lefname = curpath + leffile
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lefname = OPTS.openram_temp + leffile
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s.gds_write(gdsname)
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s.gds_write(gdsname)
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lef.lef(gdsname,lefname,s)
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lef.lef(gdsname,lefname,s)
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@ -32,9 +32,8 @@ class verilog_test(unittest.TestCase):
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OPTS.check_lvsdrc = True
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OPTS.check_lvsdrc = True
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curpath=os.path.dirname(os.path.realpath(__file__)) + "/"
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vfile = s.name + ".v"
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vfile = s.name + ".v"
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vname = curpath + vfile
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vname = OPTS.openram_temp + vfile
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verilog.verilog(vname,s)
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verilog.verilog(vname,s)
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