Output number of words per row before SRAM creation. Recompute words per row in unit tests.

compiler/openram.py

@@ -26,6 +26,10 @@ if len(args) != 1:
 # These depend on arguments, so don't load them until now.
 import debug
 
+# Keep track of running stats
+start_time = datetime.datetime.now()
+print_time("Start",start_time)
+
 init_openram(config_file=args[0], is_unit_test=False)
 
 # Only print banner here so it's not in unit tests
@@ -34,10 +38,14 @@ print_banner()
 # Output info about this run
 report_status()
 
-# Start importing design modules after we have the config file
-import verify
-from sram import sram
 from sram_config import sram_config
+
+
+# Configure the SRAM organization
+c = sram_config(word_size=OPTS.word_size,
+                num_words=OPTS.num_words)
+print("Words per row: {}".format(c.words_per_row))
+
 #from parser import *
 output_extensions = ["sp","v","lib"]
 if OPTS.datasheet_gen:
@@ -48,15 +56,8 @@ output_files = ["{0}.{1}".format(OPTS.output_name,x) for x in output_extensions]
 print("Output files are: ")
 print(*output_files,sep="\n")
 
-# Keep track of running stats
-start_time = datetime.datetime.now()
-print_time("Start",start_time)
 
-# Configure the SRAM organization
+from sram import sram
-c = sram_config(word_size=OPTS.word_size,
-                num_words=OPTS.num_words)
-
-# import SRAM test generation
 s = sram(sram_config=c,
          name=OPTS.output_name)
 

compiler/sram.py

@@ -14,7 +14,6 @@ class sram():
     """
     def __init__(self, sram_config, name):
 
-        sram_config.compute_sizes()
         sram_config.set_local_config(self)
         
         # reset the static duplicate name checker for unit tests

compiler/sram_config.py

@@ -14,7 +14,7 @@ class sram_config:
         # This will get over-written when we determine the organization
         self.words_per_row = None
 
-        # Move the module names to this?
+        self.compute_sizes()
         
 
     def set_local_config(self, module):
@@ -54,6 +54,20 @@ class sram_config:
             self.tentative_num_rows = self.num_bits_per_bank / (self.words_per_row*self.word_size)
             self.words_per_row = self.amend_words_per_row(self.tentative_num_rows, self.words_per_row)
 
+        debug.info(1,"Words per row: {}".format(self.words_per_row))
+        self.recompute_sizes()
+
+    def recompute_sizes(self):
+        """ 
+        Calculate the auxiliary values assuming fixed number of words per row. 
+        This can be called multiple times from the unit test when we reconfigure an 
+        SRAM for testing.
+        """
+
+        # If the banks changed
+        self.num_words_per_bank = self.num_words/self.num_banks
+        self.num_bits_per_bank = self.word_size*self.num_words_per_bank
+        
         # Fix the number of columns and rows
         self.num_cols = int(self.words_per_row*self.word_size)
         self.num_rows = int(self.num_words_per_bank/self.words_per_row)
@@ -64,7 +78,6 @@ class sram_config:
         self.bank_addr_size = self.col_addr_size + self.row_addr_size
         self.addr_size = self.bank_addr_size + int(log(self.num_banks, 2))
 
-        debug.info(1,"Words per row: {}".format(self.words_per_row))
 
     def estimate_words_per_row(self,tentative_num_cols, word_size):
         """
@@ -76,6 +89,8 @@ class sram_config:
             return 1
         elif tentative_num_cols > 3*word_size:
             return 4
+        elif tentative_num_cols > 6*word_size:
+            return 8
         else:
             return 2
 

compiler/tests/19_multi_bank_test.py

@@ -24,18 +24,21 @@ class multi_bank_test(openram_test):
         c.num_banks=2
 
         c.words_per_row=1
+        c.recompute_sizes()
         debug.info(1, "No column mux")
         a = bank(c, name="bank1_multi")
         self.local_check(a)
 
         c.num_words=32
         c.words_per_row=2
+        c.recompute_sizes()
         debug.info(1, "Two way column mux")
         a = bank(c, name="bank2_multi")
         self.local_check(a)
 
         c.num_words=64
         c.words_per_row=4
+        c.recompute_sizes()
         debug.info(1, "Four way column mux")
         a = bank(c, name="bank3_multi")
         self.local_check(a)
@@ -43,6 +46,7 @@ class multi_bank_test(openram_test):
         c.word_size=2
         c.num_words=128
         c.words_per_row=8
+        c.recompute_sizes()
         debug.info(1, "Eight way column mux")
         a = bank(c, name="bank4_multi")
         self.local_check(a)

compiler/tests/19_psingle_bank_test.py

@@ -31,6 +31,7 @@ class psingle_bank_test(openram_test):
                         num_words=16)
         
         c.words_per_row=1
+        c.recompute_sizes()
         debug.info(1, "No column mux")
         name = "bank1_{0}rw_{1}w_{2}r_single".format(OPTS.num_rw_ports, OPTS.num_w_ports, OPTS.num_r_ports)
         a = bank(c, name=name)
@@ -38,6 +39,7 @@ class psingle_bank_test(openram_test):
         
         c.num_words=32
         c.words_per_row=2
+        c.recompute_sizes()
         debug.info(1, "Two way column mux")
         name = "bank2_{0}rw_{1}w_{2}r_single".format(OPTS.num_rw_ports, OPTS.num_w_ports, OPTS.num_r_ports)
         a = bank(c, name=name)
@@ -45,6 +47,7 @@ class psingle_bank_test(openram_test):
         
         c.num_words=64
         c.words_per_row=4
+        c.recompute_sizes()
         debug.info(1, "Four way column mux")
         name = "bank3_{0}rw_{1}w_{2}r_single".format(OPTS.num_rw_ports, OPTS.num_w_ports, OPTS.num_r_ports)
         a = bank(c, name=name)
@@ -53,6 +56,7 @@ class psingle_bank_test(openram_test):
         c.word_size=2
         c.num_words=128
         c.words_per_row=8
+        c.recompute_sizes()
         debug.info(1, "Four way column mux")
         name = "bank4_{0}rw_{1}w_{2}r_single".format(OPTS.num_rw_ports, OPTS.num_w_ports, OPTS.num_r_ports)
         a = bank(c, name=name)

compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py

@@ -30,6 +30,7 @@ class psram_1bank_2mux_1rw_1w_test(openram_test):
                         num_banks=1)
         c.num_words=32
         c.words_per_row=2
+        c.recompute_sizes()
         debug.info(1, "Layout test for {}rw,{}r,{}w psram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports,
                                                                                                                           OPTS.num_r_ports,
                                                                                                                           OPTS.num_w_ports,

compiler/tests/20_psram_1bank_2mux_1w_1r_test.py

@@ -30,6 +30,7 @@ class psram_1bank_2mux_1w_1r_test(openram_test):
                         num_banks=1)
         c.num_words=32
         c.words_per_row=2
+        c.recompute_sizes()
         debug.info(1, "Layout test for {}rw,{}r,{}w psram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports,
                                                                                                                           OPTS.num_r_ports,
                                                                                                                           OPTS.num_w_ports,

compiler/tests/20_psram_1bank_2mux_test.py

@@ -31,6 +31,7 @@ class psram_1bank_2mux_test(openram_test):
                         num_banks=1)
         c.num_words=32
         c.words_per_row=2
+        c.recompute_sizes()
         debug.info(1, "Layout test for {}rw,{}r,{}w psram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports,
                                                                                                                           OPTS.num_r_ports,
                                                                                                                           OPTS.num_w_ports,

compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py

@@ -29,6 +29,7 @@ class psram_1bank_4mux_1rw_1r_test(openram_test):
                         num_banks=1)
         c.num_words=64
         c.words_per_row=4
+        c.recompute_sizes()
         debug.info(1, "Layout test for {}rw,{}r,{}w psram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports,
                                                                                                                           OPTS.num_r_ports,
                                                                                                                           OPTS.num_w_ports,

compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py

@@ -29,6 +29,7 @@ class sram_1bank_2mux_1rw_1r_test(openram_test):
                         num_banks=1)
 
         c.words_per_row=2
+        c.recompute_sizes()
         debug.info(1, "Layout test for {}rw,{}r,{}w sram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports,
                                                                                                                          OPTS.num_r_ports,
                                                                                                                          OPTS.num_w_ports,

compiler/tests/20_sram_1bank_2mux_test.py

@@ -23,6 +23,7 @@ class sram_1bank_2mux_test(openram_test):
                         num_banks=1)
 
         c.words_per_row=2
+        c.recompute_sizes()
         debug.info(1, "Layout test for {}rw,{}r,{}w sram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports,
                                                                                                                          OPTS.num_r_ports,
                                                                                                                          OPTS.num_w_ports,

compiler/tests/20_sram_1bank_4mux_test.py

@@ -23,6 +23,7 @@ class sram_1bank_4mux_test(openram_test):
                         num_banks=1)
 
         c.words_per_row=4
+        c.recompute_sizes()
         debug.info(1, "Layout test for {}rw,{}r,{}w sram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports,
                                                                                                                          OPTS.num_r_ports,
                                                                                                                          OPTS.num_w_ports,

compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py

@@ -29,6 +29,7 @@ class sram_1bank_8mux_1rw_1r_test(openram_test):
                         num_banks=1)
 
         c.words_per_row=8
+        c.recompute_sizes()
         debug.info(1, "Layout test for {}rw,{}r,{}w sram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports,
                                                                                                                          OPTS.num_r_ports,
                                                                                                                          OPTS.num_w_ports,

compiler/tests/20_sram_1bank_8mux_test.py

@@ -23,6 +23,7 @@ class sram_1bank_8mux_test(openram_test):
                         num_banks=1)
 
         c.words_per_row=8
+        c.recompute_sizes()
         debug.info(1, "Layout test for {}rw,{}r,{}w sram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports,
                                                                                                                          OPTS.num_r_ports,
                                                                                                                          OPTS.num_w_ports,

compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py

@@ -29,6 +29,7 @@ class sram_1bank_nomux_1rw_1r_test(openram_test):
                         num_banks=1)
 
         c.words_per_row=1
+        c.recompute_sizes()
         debug.info(1, "Layout test for {}rw,{}r,{}w sram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports,
                                                                                                                          OPTS.num_r_ports,
                                                                                                                          OPTS.num_w_ports,

compiler/tests/20_sram_1bank_nomux_test.py

@@ -23,6 +23,7 @@ class sram_1bank_nomux_test(openram_test):
                         num_banks=1)
 
         c.words_per_row=1
+        c.recompute_sizes()
         debug.info(1, "Layout test for {}rw,{}r,{}w sram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports,
                                                                                                                          OPTS.num_r_ports,
                                                                                                                          OPTS.num_w_ports,

compiler/tests/20_sram_2bank_test.py

@@ -23,18 +23,21 @@ class sram_2bank_test(openram_test):
                         num_banks=2)
 
         c.words_per_row=1
+        c.recompute_sizes()
         debug.info(1, "Two bank, no column mux with control logic")
         a = sram(c, "sram1")
         self.local_check(a, final_verification=True)
 
         c.num_words=64
         c.words_per_row=2
+        c.recompute_sizes()
         debug.info(1, "Two bank two way column mux with control logic")
         a = sram(c, "sram2")
         self.local_check(a, final_verification=True)
 
         c.num_words=128
         c.words_per_row=4
+        c.recompute_sizes()
         debug.info(1, "Two bank, four way column mux with control logic")
         a = sram(c, "sram3")
         self.local_check(a, final_verification=True)
@@ -42,6 +45,7 @@ class sram_2bank_test(openram_test):
         c.word_size=2
         c.num_words=256
         c.words_per_row=8
+        c.recompute_sizes()
         debug.info(1, "Two bank, eight way column mux with control logic")
         a = sram(c, "sram4")
         self.local_check(a, final_verification=True)

compiler/tests/21_hspice_delay_test.py

@@ -30,6 +30,7 @@ class timing_sram_test(openram_test):
                         num_words=16,
                         num_banks=1)
         c.words_per_row=1
+        c.recompute_sizes()
         debug.info(1, "Testing timing for sample 1bit, 16words SRAM with 1 bank")
         s = sram(c, name="sram1")
 

compiler/tests/21_ngspice_delay_test.py

@@ -30,6 +30,7 @@ class timing_sram_test(openram_test):
                         num_words=16,
                         num_banks=1)
         c.words_per_row=1
+        c.recompute_sizes()
         debug.info(1, "Testing timing for sample 1bit, 16words SRAM with 1 bank")
         s = sram(c, name="sram1")
 

compiler/tests/22_psram_1bank_2mux_func_test.py

@@ -35,6 +35,7 @@ class psram_1bank_2mux_1rw_1r_1w_func_test(openram_test):
                         num_words=64,
                         num_banks=1)
         c.words_per_row=2
+        c.recompute_sizes()
         debug.info(1, "Functional test for {}rw,{}r,{}w psram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports,
                                                                                                                               OPTS.num_r_ports,
                                                                                                                               OPTS.num_w_ports,

compiler/tests/22_psram_1bank_4mux_func_test.py

@@ -35,6 +35,7 @@ class psram_1bank_4mux_func_test(openram_test):
                         num_words=256,
                         num_banks=1)
         c.words_per_row=4
+        c.recompute_sizes()
         debug.info(1, "Functional test for {}rw,{}r,{}w psram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports,
                                                                                                                               OPTS.num_r_ports,
                                                                                                                               OPTS.num_w_ports,

compiler/tests/22_psram_1bank_8mux_func_test.py

@@ -35,6 +35,7 @@ class psram_1bank_8mux_func_test(openram_test):
                         num_words=256,
                         num_banks=1)
         c.words_per_row=8
+        c.recompute_sizes()
         debug.info(1, "Functional test for {}rw,{}r,{}w psram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports,
                                                                                                                               OPTS.num_r_ports,
                                                                                                                               OPTS.num_w_ports,

compiler/tests/22_psram_1bank_nomux_func_test.py

@@ -35,6 +35,7 @@ class psram_1bank_nomux_func_test(openram_test):
                         num_words=32,
                         num_banks=1)
         c.words_per_row=1
+        c.recompute_sizes()
         debug.info(1, "Functional test for {}rw,{}r,{}w psram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports,
                                                                                                                               OPTS.num_r_ports,
                                                                                                                               OPTS.num_w_ports,

compiler/tests/22_sram_1bank_2mux_func_test.py

@@ -30,6 +30,7 @@ class sram_1bank_2mux_func_test(openram_test):
                         num_words=64,
                         num_banks=1)
         c.words_per_row=2
+        c.recompute_sizes()
         debug.info(1, "Functional test for sram with {} bit words, {} words, {} words per row, {} banks".format(c.word_size,
                                                                                                                 c.num_words,
                                                                                                                 c.words_per_row,

compiler/tests/22_sram_1bank_4mux_func_test.py

@@ -30,6 +30,7 @@ class sram_1bank_4mux_func_test(openram_test):
                         num_words=256,
                         num_banks=1)
         c.words_per_row=4
+        c.recompute_sizes()
         debug.info(1, "Functional test for sram with {} bit words, {} words, {} words per row, {} banks".format(c.word_size,
                                                                                                                 c.num_words,
                                                                                                                 c.words_per_row,

compiler/tests/22_sram_1bank_8mux_func_test.py

@@ -33,6 +33,7 @@ class sram_1bank_8mux_func_test(openram_test):
                         num_words=256,
                         num_banks=1)
         c.words_per_row=8
+        c.recompute_sizes()
         debug.info(1, "Functional test for sram with {} bit words, {} words, {} words per row, {} banks".format(c.word_size,
                                                                                                                 c.num_words,
                                                                                                                 c.words_per_row,

compiler/tests/22_sram_1bank_nomux_func_test.py

@@ -30,6 +30,7 @@ class sram_1bank_nomux_func_test(openram_test):
                         num_words=32,
                         num_banks=1)
         c.words_per_row=1
+        c.recompute_sizes()
         debug.info(1, "Functional test for sram with {} bit words, {} words, {} words per row, {} banks".format(c.word_size,
                                                                                                                 c.num_words,
                                                                                                                 c.words_per_row,

compiler/tests/22_sram_1rw_1r_1bank_nomux_func_test.py

@@ -35,6 +35,7 @@ class psram_1bank_nomux_func_test(openram_test):
                         num_words=32,
                         num_banks=1)
         c.words_per_row=1
+        c.recompute_sizes()
         debug.info(1, "Functional test for sram 1rw,1r with {} bit words, {} words, {} words per row, {} banks".format(c.word_size,
                                                                                                                 c.num_words,
                                                                                                                 c.words_per_row,

compiler/tests/23_lib_sram_model_test.py

@@ -23,6 +23,7 @@ class lib_test(openram_test):
                         num_words=16,
                         num_banks=1)
         c.words_per_row=1
+        c.recompute_sizes()
         debug.info(1, "Testing analytical timing for sample 2 bit, 16 words SRAM with 1 bank")
         s = sram(c, "sram_2_16_1_{0}".format(OPTS.tech_name))
         tempspice = OPTS.openram_temp + "temp.sp"

compiler/tests/23_lib_sram_prune_test.py

@@ -32,6 +32,7 @@ class lib_test(openram_test):
                         num_words=16,
                         num_banks=1)
         c.words_per_row=1
+        c.recompute_sizes()
         debug.info(1, "Testing pruned timing for sample 2 bit, 16 words SRAM with 1 bank")
         s = sram(c, "sram_2_16_1_{0}".format(OPTS.tech_name))
 

compiler/tests/23_lib_sram_test.py

@@ -32,6 +32,7 @@ class lib_test(openram_test):
                         num_words=16,
                         num_banks=1)
         c.words_per_row=1
+        c.recompute_sizes()
         debug.info(1, "Testing timing for sample 2 bit, 16 words SRAM with 1 bank")
         s = sram(c, "sram_2_16_1_{0}".format(OPTS.tech_name))
 

compiler/tests/24_lef_sram_test.py

@@ -23,6 +23,7 @@ class lef_test(openram_test):
                         num_words=16,
                         num_banks=1)
         c.words_per_row=1
+        c.recompute_sizes()
         debug.info(1, "Testing LEF for sample 2 bit, 16 words SRAM with 1 bank")
         s = sram(c, "sram_2_16_1_{0}".format(OPTS.tech_name))
 

compiler/tests/25_verilog_sram_test.py

@@ -22,6 +22,7 @@ class verilog_test(openram_test):
                         num_words=16,
                         num_banks=1)
         c.words_per_row=1
+        c.recompute_sizes()
         debug.info(1, "Testing Verilog for sample 2 bit, 16 words SRAM with 1 bank")
         s = sram(c, "sram_2_16_1_{0}".format(OPTS.tech_name))
 

compiler/tests/27_worst_case_delay_test.py

@@ -39,7 +39,7 @@ class worst_case_timing_sram_test(openram_test):
                         num_words=num_words,
                         num_banks=num_banks)
         c.words_per_row=1
-        #c.compute_sizes()
+        c.recompute_sizes()
         debug.info(1, "Testing the timing different bitecells inside a {}bit, {} words SRAM with {} bank".format(
                                                                        word_size, num_words, num_banks))
         s = sram(c, name="sram1")