mirror of https://github.com/VLSIDA/OpenRAM.git
Change bitcell array name to match
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@ -17,7 +17,7 @@ import debug
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#@unittest.skip("SKIPPING 05_bitcell_1rw_1r_array_test")
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#@unittest.skip("SKIPPING 05_bitcell_1rw_1r_array_test")
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class bitcell_1rw_1r_array_test(openram_test):
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class bitcell_array_1rw_1r_test(openram_test):
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def runTest(self):
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def runTest(self):
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config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
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config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
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