From 469cd260b954cd191a9291eca69e61170dbf2bea Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 10 Jun 2020 14:54:20 -0700 Subject: [PATCH] Change bitcell array name to match --- ...ell_1rw_1r_array_test.py => 05_bitcell_array_1rw_1r_test.py} | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) rename compiler/tests/{05_bitcell_1rw_1r_array_test.py => 05_bitcell_array_1rw_1r_test.py} (96%) diff --git a/compiler/tests/05_bitcell_1rw_1r_array_test.py b/compiler/tests/05_bitcell_array_1rw_1r_test.py similarity index 96% rename from compiler/tests/05_bitcell_1rw_1r_array_test.py rename to compiler/tests/05_bitcell_array_1rw_1r_test.py index 0683d127..0e7d5665 100755 --- a/compiler/tests/05_bitcell_1rw_1r_array_test.py +++ b/compiler/tests/05_bitcell_array_1rw_1r_test.py @@ -17,7 +17,7 @@ import debug #@unittest.skip("SKIPPING 05_bitcell_1rw_1r_array_test") -class bitcell_1rw_1r_array_test(openram_test): +class bitcell_array_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))