From 468c972acb23036062c69712c9759c2ffa2d2c96 Mon Sep 17 00:00:00 2001 From: Sam Crow Date: Wed, 5 Jul 2023 16:08:38 -0700 Subject: [PATCH] add optional guard band to delay chain sizing --- compiler/modules/control_logic_delay.py | 9 +++++++-- compiler/options.py | 8 ++++++-- 2 files changed, 13 insertions(+), 4 deletions(-) diff --git a/compiler/modules/control_logic_delay.py b/compiler/modules/control_logic_delay.py index b5bbe4b4..b980d9eb 100644 --- a/compiler/modules/control_logic_delay.py +++ b/compiler/modules/control_logic_delay.py @@ -142,21 +142,26 @@ class control_logic_delay(control_logic_base): # time for bitline to drop from vdd by threshold voltage once wordline enabled bitline_vth_swing = (spice["nom_supply_voltage"] - spice["nom_threshold"]) / spice["nom_supply_voltage"] bitline_vth_delay = abs(math.log(1 - bitline_vth_swing)) * spice["wire_unit_r"] * bitline_area * bitline_cap_ff - print("delays: delay_stage {} precharge {} pen {} wl {} wlen {} vth {}".format(inverter_stage_delay, precharge_delay, pen_signal_delay, wordline_delay, wlen_signal_delay, bitline_vth_delay)) + # print("delays: delay_stage {} precharge {} pen {} wl {} wlen {} vth {}".format(inverter_stage_delay, precharge_delay, pen_signal_delay, wordline_delay, wlen_signal_delay, bitline_vth_delay)) delays = [None] * 5 # keepout between p_en rising and wl_en falling - delays[0] = int((wlen_signal_delay + wordline_delay) / inverter_stage_delay) # could possibly subtract pen_signal_delay? + delays[0] = (wlen_signal_delay + wordline_delay) / inverter_stage_delay # could possibly subtract pen_signal_delay? + delays[0] = int(delays[0] * OPTS.delay_control_scaling_factor) + # round up to nearest even integer delays[0] += delays[0] % 2 delays[2] = delays[0] + (pen_signal_delay + precharge_delay) / inverter_stage_delay + delays[2] *= OPTS.delay_control_scaling_factor # round up to nearest odd integer delays[2] = int(1 - (2 * ((1 - delays[2]) // 2))) # delays[1] can be any even value less than delays[2] delays[1] = delays[2] - 1 # keepout between p_en falling and wl_en rising delays[3] = delays[2] + pen_signal_delay / inverter_stage_delay + delays[3] *= OPTS.delay_control_scaling_factor delays[3] = int(1 - (2 * ((1 - delays[3]) // 2))) delays[4] = delays[3] + (wlen_signal_delay + wordline_delay + bitline_vth_delay) / inverter_stage_delay + delays[4] *= OPTS.delay_control_scaling_factor delays[4] = int(1 - (2 * ((1 - delays[4]) // 2))) self.delay_chain_pinout_list = delays # FIXME: fanout should be used to control delay chain height diff --git a/compiler/options.py b/compiler/options.py index 92427ac0..d7fc74b3 100644 --- a/compiler/options.py +++ b/compiler/options.py @@ -67,9 +67,13 @@ class options(optparse.Values): # Approximate percentage of delay compared to bitlines rbl_delay_percentage = 0.5 - # Allow manual adjustment of the delay chain over automatic - auto_delay_chain_sizing = False + # delay chain is automatically sized in delay based control logic + # this multiplier can be used to add a guard band to the standard timing + # lowering it can improve performance but may cause sram to fail + delay_control_scaling_factor = 1.0 + # stages for delay chain in rbl control logic only delay_chain_stages = 9 + # fanout per stage for any control logic delay_chain_fanout_per_stage = 4 accuracy_requirement = 0.75