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https://github.com/VLSIDA/OpenRAM.git
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Replica bitcell array working
This commit is contained in:
mrg
@@ -270,13 +270,15 @@ class bank(design.design):
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# the bitcell array.
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# The decoder/driver logic is placed on the right and mirrored on Y-axis.
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# The write/sense/precharge/mux is placed on the top and mirrored on the X-axis.
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bitcell_array_top = self.bitcell_array.height + self.m2_gap + drc("well_enclosure_active") + self.m1_width
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bitcell_array_right = self.bitcell_array.width + self.m1_width + self.m2_gap
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# LOWER LEFT QUADRANT
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# Bitcell array is placed at (0,0)
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# UPPER LEFT QUADRANT
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# Above the bitcell array
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y_offset = self.bitcell_array.height + self.m2_gap
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y_offset = bitcell_array_top
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for i,p in enumerate(self.vertical_port_order[port]):
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if p==None:
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continue
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@@ -292,7 +294,7 @@ class bank(design.design):
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# LOWER RIGHT QUADRANT
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# To the left of the bitcell array
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# The wordline driver is placed to the right of the main decoder width.
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x_offset = self.bitcell_array.width + self.m2_gap + self.wordline_driver.width
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x_offset = bitcell_array_right + self.wordline_driver.width
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self.wordline_driver_offsets[port] = vector(x_offset,0)
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x_offset += self.row_decoder.width + self.m2_gap
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self.row_decoder_offsets[port] = vector(x_offset,0)
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@@ -300,12 +302,12 @@ class bank(design.design):
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# UPPER RIGHT QUADRANT
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# Place the col decoder right aligned with wordline driver plus halfway under row decoder
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# Above the bitcell array with a well spacing
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x_offset = self.bitcell_array.width + self.central_bus_width[port] + self.wordline_driver.width
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x_offset = bitcell_array_right + self.central_bus_width[port] + self.wordline_driver.width
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if self.col_addr_size > 0:
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x_offset += self.column_decoder.width + self.col_addr_bus_width
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y_offset = self.bitcell_array.height + self.column_decoder.height + self.m2_gap
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y_offset = bitcell_array_height + self.column_decoder.height
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else:
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y_offset = self.bitcell_array.height
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y_offset = bitcell_array_height
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y_offset += 2*drc("well_to_well")
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self.column_decoder_offsets[port] = vector(x_offset,y_offset)
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@@ -860,8 +862,8 @@ class bank(design.design):
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# Port 1
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if len(self.all_ports)==2:
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# The other control bus is routed up to two pitches above the bitcell array
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control_bus_length = self.max_y_offset - self.bitcell_array.height - 2*self.m1_pitch
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control_bus_offset = vector(self.bitcell_array.width + self.m2_width,
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control_bus_length = self.max_y_offset - bitcell_array_top - 2*self.m1_pitch
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control_bus_offset = vector(bitcell_array_right,
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self.max_y_offset - control_bus_length)
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self.bus_xoffset[1] = self.create_bus(layer="metal2",
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@@ -45,8 +45,8 @@ class bitcell_array(design.design):
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def create_layout(self):
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# We increase it by a well enclosure so the precharges don't overlap our wells
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self.height = self.row_size*self.cell.height + drc("well_enclosure_active") + self.m1_width
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self.width = self.column_size*self.cell.width + self.m1_width
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self.height = self.row_size*self.cell.height
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self.width = self.column_size*self.cell.width
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xoffset = 0.0
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for col in range(self.column_size):
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@@ -89,6 +89,24 @@ class bitcell_array(design.design):
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self.cell = factory.create(module_type="bitcell")
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self.add_mod(self.cell)
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def list_bitcell_pins(self, col, row):
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""" Creates a list of connections in the bitcell,
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indexed by column and row, for instance use in bitcell_array """
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bitcell_pins = []
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pin_names = self.cell.list_all_bitline_names()
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for pin in pin_names:
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bitcell_pins.append(pin+"_{0}".format(col))
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pin_names = self.cell.list_all_wl_names()
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for pin in pin_names:
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bitcell_pins.append(pin+"_{0}".format(row))
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bitcell_pins.append("vdd")
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bitcell_pins.append("gnd")
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return bitcell_pins
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def create_instances(self):
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""" Create the module instances used in this design """
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self.cell_inst = {}
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@@ -97,7 +115,7 @@ class bitcell_array(design.design):
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name = "bit_r{0}_c{1}".format(row, col)
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self.cell_inst[row,col]=self.add_inst(name=name,
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mod=self.cell)
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self.connect_inst(self.cell.list_bitcell_pins(col, row))
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self.connect_inst(self.list_bitcell_pins(col, row))
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def add_layout_pins(self):
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""" Add the layout pins """
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@@ -105,32 +123,24 @@ class bitcell_array(design.design):
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row_list = self.cell.list_all_wl_names()
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column_list = self.cell.list_all_bitline_names()
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offset = vector(0.0, 0.0)
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for col in range(self.column_size):
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for cell_column in column_list:
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bl_pin = self.cell_inst[0,col].get_pin(cell_column)
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self.add_layout_pin(text=cell_column+"_{0}".format(col),
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layer="metal2",
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offset=bl_pin.ll(),
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layer=bl_pin.layer,
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offset=bl_pin.ll().scale(1,0),
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width=bl_pin.width(),
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height=self.height)
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# increments to the next column width
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offset.x += self.cell.width
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offset.x = 0.0
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for row in range(self.row_size):
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for cell_row in row_list:
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wl_pin = self.cell_inst[row,0].get_pin(cell_row)
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self.add_layout_pin(text=cell_row+"_{0}".format(row),
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layer="metal1",
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offset=wl_pin.ll(),
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layer=wl_pin.layer,
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offset=wl_pin.ll().scale(0,1),
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width=self.width,
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height=wl_pin.height())
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# increments to the next row height
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offset.y += self.cell.height
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# For every second row and column, add a via for gnd and vdd
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for row in range(self.row_size):
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for col in range(self.column_size):
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@@ -0,0 +1,156 @@
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California
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# All rights reserved.
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#
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import debug
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import design
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from tech import drc
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import contact
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from sram_factory import factory
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from vector import vector
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from globals import OPTS
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class dummy_array(design.design):
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"""
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Generate a dummy row/column for the replica array.
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"""
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def __init__(self, cols, rows, name):
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design.design.__init__(self, name)
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debug.info(1, "Creating {0} {1} x {2}".format(self.name, rows, cols))
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self.add_comment("rows: {0} cols: {1}".format(rows, cols))
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self.column_size = cols
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self.row_size = rows
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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def create_netlist(self):
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""" Create and connect the netlist """
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self.add_modules()
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self.add_pins()
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self.create_instances()
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def create_layout(self):
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# We increase it by a well enclosure so the precharges don't overlap our wells
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self.height = self.row_size*self.dummy_cell.height
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self.width = self.column_size*self.dummy_cell.width
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xoffset = 0.0
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for col in range(self.column_size):
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yoffset = 0.0
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for row in range(self.row_size):
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name = "dummy_r{0}_c{1}".format(row, col)
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if row % 2:
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tempy = yoffset + self.dummy_cell.height
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dir_key = "MX"
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else:
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tempy = yoffset
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dir_key = ""
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self.cell_inst[row,col].place(offset=[xoffset, tempy],
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mirror=dir_key)
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yoffset += self.dummy_cell.height
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xoffset += self.dummy_cell.width
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self.add_layout_pins()
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self.add_boundary()
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self.DRC_LVS()
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def add_pins(self):
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row_list = self.cell.list_all_wl_names()
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column_list = self.cell.list_all_bitline_names()
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for col in range(self.column_size):
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for cell_column in column_list:
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self.add_pin(cell_column+"_{0}".format(col))
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for row in range(self.row_size):
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for cell_row in row_list:
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self.add_pin(cell_row+"_{0}".format(row))
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self.add_pin("vdd")
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self.add_pin("gnd")
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def add_modules(self):
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""" Add the modules used in this design """
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self.dummy_cell = factory.create(module_type="dummy_bitcell")
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self.add_mod(self.dummy_cell)
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self.cell = factory.create(module_type="bitcell")
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def list_bitcell_pins(self, col, row):
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""" Creates a list of connections in the bitcell,
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indexed by column and row, for instance use in bitcell_array """
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bitcell_pins = []
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pin_names = self.cell.list_all_bitline_names()
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for pin in pin_names:
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bitcell_pins.append(pin+"_{0}".format(col))
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pin_names = self.cell.list_all_wl_names()
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for pin in pin_names:
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bitcell_pins.append(pin+"_{0}".format(row))
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bitcell_pins.append("vdd")
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bitcell_pins.append("gnd")
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return bitcell_pins
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def create_instances(self):
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""" Create the module instances used in this design """
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self.cell_inst = {}
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for col in range(self.column_size):
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for row in range(self.row_size):
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name = "bit_r{0}_c{1}".format(row, col)
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self.cell_inst[row,col]=self.add_inst(name=name,
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mod=self.dummy_cell)
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self.connect_inst(self.list_bitcell_pins(col, row))
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def add_layout_pins(self):
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""" Add the layout pins """
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row_list = self.cell.list_all_wl_names()
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column_list = self.cell.list_all_bitline_names()
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for col in range(self.column_size):
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for cell_column in column_list:
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bl_pin = self.cell_inst[0,col].get_pin(cell_column)
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self.add_layout_pin(text=cell_column+"_{0}".format(col),
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layer="metal2",
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offset=bl_pin.ll(),
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width=bl_pin.width(),
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height=self.height)
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for row in range(self.row_size):
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for cell_row in row_list:
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wl_pin = self.cell_inst[row,0].get_pin(cell_row)
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self.add_layout_pin(text=cell_row+"_{0}".format(row),
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layer="metal1",
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offset=wl_pin.ll(),
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width=self.width,
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height=wl_pin.height())
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# For every second row and column, add a via for gnd and vdd
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for row in range(self.row_size):
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for col in range(self.column_size):
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inst = self.cell_inst[row,col]
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for pin_name in ["vdd", "gnd"]:
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for pin in inst.get_pins(pin_name):
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self.add_power_pin(name=pin_name, loc=pin.center(), vertical=True, start_layer=pin.layer)
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def input_load(self):
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wl_wire = self.gen_wl_wire()
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return wl_wire.return_input_cap()
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def get_wordline_cin(self):
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"""Get the relative input capacitance from the wordline connections in all the bitcell"""
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#A single wordline is connected to all the bitcells in a single row meaning the capacitance depends on the # of columns
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bitcell_wl_cin = self.cell.get_wl_cin()
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total_cin = bitcell_wl_cin * self.column_size
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return total_cin
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@@ -1,133 +0,0 @@
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California
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# All rights reserved.
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#
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import debug
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import design
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from tech import drc
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import contact
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from sram_factory import factory
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from vector import vector
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from globals import OPTS
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class dummy_row(design.design):
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"""
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Generate a replica wordline row for the replica array.
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"""
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def __init__(self, name, cols):
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design.design.__init__(self, name)
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self.column_size = cols
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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def create_netlist(self):
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self.add_modules()
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self.add_pins()
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self.create_instances()
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def create_layout(self):
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self.place_instances()
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self.add_layout_pins()
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self.add_boundary()
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self.DRC_LVS()
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def add_pins(self):
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column_list = self.cell.list_all_bitline_names()
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for col in range(self.column_size):
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for cell_column in column_list:
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self.add_pin("{0}_{1}".format(cell_column,col))
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row_list = self.cell.list_all_wl_names()
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for cell_row in row_list:
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self.add_pin("{0}_{1}".format(cell_row,0))
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self.add_pin("vdd")
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self.add_pin("gnd")
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def add_modules(self):
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self.dummy_cell = factory.create(module_type="dummy_bitcell")
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self.add_mod(self.dummy_cell)
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# Used for pin names only
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self.cell = factory.create(module_type="bitcell")
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def create_instances(self):
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self.cell_inst = {}
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for col in range(self.column_size):
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name="dummy_{0}".format(col)
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self.cell_inst[col]=self.add_inst(name=name,
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mod=self.dummy_cell)
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self.connect_inst(self.list_bitcell_pins(col, 0))
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def create_layout(self):
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# We increase it by a well enclosure so the precharges don't overlap our wells
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self.height = self.cell.height
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self.width = self.column_size*self.cell.width
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xoffset = 0.0
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tempy = self.cell.height
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dir_key = "MX"
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for col in range(self.column_size):
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name = "bit_{0}_c{1}".format("dummy",col)
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self.cell_inst[col].place(offset=[xoffset, tempy],
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mirror=dir_key)
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xoffset += self.cell.width
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self.add_layout_pins()
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self.add_boundary()
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self.DRC_LVS()
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def add_layout_pins(self):
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""" Add the layout pins """
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row_list = self.cell.list_all_wl_names()
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column_list = self.cell.list_all_bitline_names()
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for col in range(self.column_size):
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for cell_column in column_list:
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bl_pin = self.cell_inst[col].get_pin(cell_column)
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self.add_layout_pin(text=cell_column+"_{0}".format(col),
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layer="metal2",
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offset=bl_pin.ll(),
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width=bl_pin.width(),
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height=self.height)
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for cell_row in row_list:
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wl_pin = self.cell_inst[0].get_pin(cell_row)
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self.add_layout_pin(text=cell_row+"_{0}".format(0),
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layer="metal1",
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offset=wl_pin.ll(),
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width=self.width,
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height=wl_pin.height())
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# For every second row and column, add a via for gnd and vdd
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for col in range(self.column_size):
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inst = self.cell_inst[col]
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for pin_name in ["vdd", "gnd"]:
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self.copy_layout_pin(inst, pin_name)
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def list_bitcell_pins(self, col, row):
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""" Creates a list of connections in the bitcell,
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indexed by column and row, for instance use in bitcell_array """
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bitcell_pins = []
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pin_names = self.cell.list_all_bitline_names()
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for pin in pin_names:
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bitcell_pins.append(pin+"_{0}".format(col))
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pin_names = self.cell.list_all_wl_names()
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for pin in pin_names:
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bitcell_pins.append(pin+"_{0}".format(row))
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bitcell_pins.append("vdd")
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bitcell_pins.append("gnd")
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return bitcell_pins
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@@ -0,0 +1,366 @@
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# See LICENSE for licensing information.
|
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#
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# Copyright (c) 2016-2019 Regents of the University of California
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# All rights reserved.
|
||||
#
|
||||
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import debug
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import design
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||||
from tech import drc, spice
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from vector import vector
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from globals import OPTS
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from sram_factory import factory
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import logical_effort
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import bitcell_array
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import replica_column
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import dummy_array
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class replica_bitcell_array(design.design):
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"""
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Creates a bitcell arrow of cols x rows and then adds the replica and dummy columns
|
||||
and rows for one or two read ports. Replica columns are on the left and right, respectively.
|
||||
Dummy are the outside columns/rows with WL and BL tied to gnd.
|
||||
Requires a regular bitcell array, replica bitcell, and dummy bitcell (Bl/BR disconnected).
|
||||
"""
|
||||
def __init__(self, cols, rows, name):
|
||||
design.design.__init__(self, name)
|
||||
debug.info(1, "Creating {0} {1} x {2}".format(self.name, rows, cols))
|
||||
self.add_comment("rows: {0} cols: {1}".format(rows, cols))
|
||||
|
||||
self.column_size = cols
|
||||
self.row_size = rows
|
||||
|
||||
self.create_netlist()
|
||||
if not OPTS.netlist_only:
|
||||
self.create_layout()
|
||||
|
||||
# We don't offset this because we need to align
|
||||
# the replica bitcell in the control logic
|
||||
#self.offset_all_coordinates()
|
||||
|
||||
|
||||
def create_netlist(self):
|
||||
""" Create and connect the netlist """
|
||||
self.add_modules()
|
||||
self.add_pins()
|
||||
self.create_instances()
|
||||
|
||||
def add_modules(self):
|
||||
""" Array and dummy/replica columns
|
||||
|
||||
d or D = dummy cell (caps to distinguish grouping)
|
||||
r or R = replica cell (caps to distinguish grouping)
|
||||
b or B = bitcell
|
||||
replica columns 1
|
||||
v v
|
||||
bdDDDDDDDDDDDDDDdb <- Dummy row
|
||||
bdDDDDDDDDDDDDDDrb <- Dummy row
|
||||
br--------------rb
|
||||
br| Array |rb
|
||||
br| row x col |rb
|
||||
br--------------rb
|
||||
brDDDDDDDDDDDDDDdb <- Dummy row
|
||||
bdDDDDDDDDDDDDDDdb <- Dummy row
|
||||
|
||||
^^^^^^^^^^^^^^^
|
||||
dummy rows cols x 1
|
||||
|
||||
^ dummy columns ^
|
||||
1 x (rows + 4)
|
||||
"""
|
||||
|
||||
# Bitcell for port names only
|
||||
self.cell = factory.create(module_type="bitcell")
|
||||
|
||||
# Bitcell array
|
||||
self.bitcell_array = factory.create(module_type="bitcell_array",
|
||||
cols=self.column_size,
|
||||
rows=self.row_size)
|
||||
self.add_mod(self.bitcell_array)
|
||||
|
||||
# Replica bitline
|
||||
self.replica_column = factory.create(module_type="replica_column",
|
||||
rows=self.row_size + 4)
|
||||
self.add_mod(self.replica_column)
|
||||
|
||||
# Dummy row
|
||||
self.dummy_row = factory.create(module_type="dummy_array",
|
||||
rows=1,
|
||||
cols=self.column_size)
|
||||
self.add_mod(self.dummy_row)
|
||||
|
||||
# Dummy col
|
||||
self.dummy_col = factory.create(module_type="dummy_array",
|
||||
cols=1,
|
||||
rows=self.row_size + 4)
|
||||
self.add_mod(self.dummy_col)
|
||||
|
||||
|
||||
|
||||
def add_pins(self):
|
||||
|
||||
self.wl_names = [x for x in self.bitcell_array.pins if x.startswith("w")]
|
||||
self.bl_names = [x for x in self.bitcell_array.pins if x.startswith("b")]
|
||||
|
||||
# top/bottom rows (in the middle)
|
||||
self.replica_wl_names = ["replica_"+x for x in self.cell.pins if x.startswith("w")]
|
||||
self.dummy_wl_names = ["dummy_"+x for x in self.cell.pins if x.startswith("w")]
|
||||
self.dummy_bl_names = ["dummy_"+x for x in self.cell.pins if x.startswith("b")]
|
||||
self.dummy_row_bl_names = self.bl_names
|
||||
|
||||
# dummy row and replica on each side of the bitcell rows
|
||||
self.replica_col_wl_names = [x+"_0" for x in self.dummy_wl_names] \
|
||||
+ ["replica_"+x+"_0" for x in self.cell.list_all_wl_names()] \
|
||||
+ self.wl_names \
|
||||
+ ["replica_"+x+"_1" for x in self.cell.list_all_wl_names()] \
|
||||
+ [x+"_1" for x in self.dummy_wl_names]
|
||||
self.replica_bl_names = ["replica_"+x for x in self.cell.pins if x.startswith("b")]
|
||||
|
||||
# left/right rows
|
||||
self.dummy_col_wl_names = self.replica_col_wl_names
|
||||
|
||||
|
||||
self.add_pin_list(self.bl_names)
|
||||
self.add_pin_list([x+"_0" for x in self.replica_bl_names])
|
||||
self.add_pin_list([x+"_1" for x in self.replica_bl_names])
|
||||
self.add_pin_list([x for x in self.replica_col_wl_names if not x.startswith("dummy")])
|
||||
|
||||
self.add_pin("vdd")
|
||||
self.add_pin("gnd")
|
||||
|
||||
|
||||
def create_instances(self):
|
||||
""" Create the module instances used in this design """
|
||||
|
||||
supplies = ["vdd", "gnd"]
|
||||
# Main array
|
||||
self.bitcell_array_inst=self.add_inst(name="bitcell_array",
|
||||
mod=self.bitcell_array)
|
||||
self.connect_inst(self.bitcell_array.pins)
|
||||
|
||||
# Replica columns (two even if one port for now)
|
||||
self.replica_col_left_inst=self.add_inst(name="replica_col_left",
|
||||
mod=self.replica_column)
|
||||
self.connect_inst([x+"_0" for x in self.replica_bl_names] + self.replica_col_wl_names + supplies)
|
||||
|
||||
self.replica_col_right_inst=self.add_inst(name="replica_col_right",
|
||||
mod=self.replica_column)
|
||||
self.connect_inst([x+"_1" for x in self.replica_bl_names] + self.replica_col_wl_names[::-1] + supplies)
|
||||
|
||||
# Replica rows with replica bitcell
|
||||
self.dummy_row_bottop_inst=self.add_inst(name="dummy_row_bottop",
|
||||
mod=self.dummy_row)
|
||||
self.connect_inst(self.dummy_row_bl_names + [x+"_0" for x in self.replica_wl_names] + supplies)
|
||||
self.dummy_row_topbot_inst=self.add_inst(name="dummy_row_topbot",
|
||||
mod=self.dummy_row)
|
||||
self.connect_inst(self.dummy_row_bl_names + [x+"_1" for x in self.replica_wl_names] + supplies)
|
||||
|
||||
|
||||
# Dummy rows without replica bitcell
|
||||
self.dummy_row_botbot_inst=self.add_inst(name="dummy_row_botbot",
|
||||
mod=self.dummy_row)
|
||||
self.connect_inst(self.dummy_row_bl_names + [x+"_0" for x in self.dummy_wl_names] + supplies)
|
||||
self.dummy_row_toptop_inst=self.add_inst(name="dummy_row_toptop",
|
||||
mod=self.dummy_row)
|
||||
self.connect_inst(self.dummy_row_bl_names + [x+"_1" for x in self.dummy_wl_names] + supplies)
|
||||
|
||||
|
||||
# Dummy columns
|
||||
self.dummy_col_left_inst=self.add_inst(name="dummy_col_left",
|
||||
mod=self.dummy_col)
|
||||
self.connect_inst([x+"_0" for x in self.dummy_bl_names] + self.dummy_col_wl_names + supplies)
|
||||
self.dummy_col_right_inst=self.add_inst(name="dummy_col_right",
|
||||
mod=self.dummy_col)
|
||||
self.connect_inst([x+"_1" for x in self.dummy_bl_names] + self.dummy_col_wl_names + supplies)
|
||||
|
||||
|
||||
|
||||
def create_layout(self):
|
||||
|
||||
self.height = (self.row_size+4)*self.dummy_row.height
|
||||
self.width = (self.column_size+4)*self.replica_column.width
|
||||
|
||||
# This is a bitcell x bitcell offset to scale
|
||||
offset = vector(self.replica_column.width, self.dummy_row.height)
|
||||
|
||||
self.bitcell_array_inst.place(offset=[0,0])
|
||||
self.replica_col_left_inst.place(offset=offset.scale(-1,-2))
|
||||
self.replica_col_right_inst.place(offset=offset.scale(0,2)+self.bitcell_array_inst.ur(),
|
||||
mirror="MX")
|
||||
|
||||
self.dummy_row_toptop_inst.place(offset=offset.scale(0,2)+self.bitcell_array_inst.ul(),
|
||||
mirror="MX")
|
||||
self.dummy_row_topbot_inst.place(offset=offset.scale(0,0)+self.bitcell_array_inst.ul())
|
||||
self.dummy_row_bottop_inst.place(offset=offset.scale(0,0),
|
||||
mirror="MX")
|
||||
self.dummy_row_botbot_inst.place(offset=offset.scale(0,-2))
|
||||
|
||||
self.dummy_col_left_inst.place(offset=offset.scale(-2,-2))
|
||||
self.dummy_col_right_inst.place(offset=offset.scale(1,-2)+self.bitcell_array_inst.lr())
|
||||
|
||||
self.translate_all(offset.scale(-2,-2))
|
||||
|
||||
self.add_layout_pins()
|
||||
|
||||
self.add_boundary()
|
||||
|
||||
self.DRC_LVS()
|
||||
|
||||
|
||||
def add_layout_pins(self):
|
||||
""" Add the layout pins """
|
||||
|
||||
# Main array wl and bl/br
|
||||
pin_names = self.bitcell_array.get_pin_names()
|
||||
for pin_name in pin_names:
|
||||
if pin_name.startswith("wl"):
|
||||
pin_list = self.bitcell_array_inst.get_pins(pin_name)
|
||||
for pin in pin_list:
|
||||
self.add_layout_pin_rect_center(text=pin_name,
|
||||
layer=pin.layer,
|
||||
offset=pin.center(),
|
||||
width=self.width,
|
||||
height=pin.height())
|
||||
elif pin_name.startswith("bl") or pin_name.startswith("br"):
|
||||
pin_list = self.bitcell_array_inst.get_pins(pin_name)
|
||||
for pin in pin_list:
|
||||
self.add_layout_pin_rect_center(text=pin_name,
|
||||
layer=pin.layer,
|
||||
offset=pin.center(),
|
||||
width=pin.width(),
|
||||
height=self.height)
|
||||
|
||||
|
||||
for index,(side1,side2) in enumerate([("bottop","left"),("topbot","right")]):
|
||||
inst = getattr(self, "dummy_row_{}_inst".format(side1))
|
||||
pin_names = inst.mod.get_pin_names()
|
||||
for pin_name in pin_names:
|
||||
if pin_name.startswith("wl"):
|
||||
pin_list = inst.get_pins(pin_name)
|
||||
for pin in pin_list:
|
||||
name = "replica_{0}_{1}".format(pin_name,index)
|
||||
self.add_layout_pin_rect_center(text=name,
|
||||
layer=pin.layer,
|
||||
offset=pin.center(),
|
||||
width=self.width,
|
||||
height=pin.height())
|
||||
|
||||
# Replica columns
|
||||
for index,side in enumerate(["left","right"]):
|
||||
inst = getattr(self, "replica_col_{}_inst".format(side))
|
||||
pin_names = inst.mod.get_pin_names()
|
||||
for pin_name in pin_names:
|
||||
if pin_name.startswith("bl") or pin_name.startswith("br"):
|
||||
pin_list = inst.get_pins(pin_name)
|
||||
for pin in pin_list:
|
||||
name = "replica_{0}_{1}".format(pin_name,index)
|
||||
self.add_layout_pin(text=name,
|
||||
layer=pin.layer,
|
||||
offset=pin.ll().scale(1,0),
|
||||
width=pin.width(),
|
||||
height=self.height)
|
||||
|
||||
|
||||
for pin_name in ["vdd","gnd"]:
|
||||
for inst in [self.bitcell_array_inst,
|
||||
self.replica_col_left_inst, self.replica_col_right_inst,
|
||||
self.dummy_col_left_inst, self.dummy_col_right_inst,
|
||||
self.dummy_row_toptop_inst, self.dummy_row_topbot_inst,
|
||||
self.dummy_row_bottop_inst, self.dummy_row_botbot_inst]:
|
||||
pin_list = inst.get_pins(pin_name)
|
||||
for pin in pin_list:
|
||||
self.add_power_pin(name=pin_name, loc=pin.center(), vertical=True, start_layer=pin.layer)
|
||||
|
||||
|
||||
# Non-pins
|
||||
|
||||
for side in ["botbot", "toptop"]:
|
||||
inst = getattr(self, "dummy_row_{}_inst".format(side))
|
||||
pin_names = inst.mod.get_pin_names()
|
||||
for pin_name in pin_names:
|
||||
if pin_name.startswith("wl"):
|
||||
pin_list = inst.get_pins(pin_name)
|
||||
for pin in pin_list:
|
||||
self.add_rect_center(layer=pin.layer,
|
||||
offset=pin.center(),
|
||||
width=self.width,
|
||||
height=pin.height())
|
||||
|
||||
|
||||
for side in ["left", "right"]:
|
||||
inst = getattr(self, "dummy_col_{}_inst".format(side))
|
||||
pin_names = inst.mod.get_pin_names()
|
||||
for pin_name in pin_names:
|
||||
if pin_name.startswith("b"):
|
||||
pin_list = inst.get_pins(pin_name)
|
||||
for pin in pin_list:
|
||||
self.add_rect_center(layer=pin.layer,
|
||||
offset=pin.center(),
|
||||
width=pin.width(),
|
||||
height=self.height)
|
||||
|
||||
|
||||
|
||||
def analytical_delay(self, corner, slew, load):
|
||||
"""Returns relative delay of the bitline in the bitcell array"""
|
||||
from tech import parameter
|
||||
#The load being driven/drained is mostly the bitline but could include the sense amp or the column mux.
|
||||
#The load from the bitlines is due to the drain capacitances from all the other bitlines and wire parasitics.
|
||||
drain_load = logical_effort.convert_farad_to_relative_c(parameter['bitcell_drain_cap'])
|
||||
wire_unit_load = .05 * drain_load #Wires add 5% to this.
|
||||
bitline_load = (drain_load+wire_unit_load)*self.row_size
|
||||
return [self.cell.analytical_delay(corner, slew, load+bitline_load)]
|
||||
|
||||
def analytical_power(self, corner, load):
|
||||
"""Power of Bitcell array and bitline in nW."""
|
||||
from tech import drc, parameter
|
||||
|
||||
# Dynamic Power from Bitline
|
||||
bl_wire = self.gen_bl_wire()
|
||||
cell_load = 2 * bl_wire.return_input_cap()
|
||||
bl_swing = parameter["rbl_height_percentage"]
|
||||
freq = spice["default_event_rate"]
|
||||
bitline_dynamic = self.calc_dynamic_power(corner, cell_load, freq, swing=bl_swing)
|
||||
|
||||
#Calculate the bitcell power which currently only includes leakage
|
||||
cell_power = self.cell.analytical_power(corner, load)
|
||||
|
||||
#Leakage power grows with entire array and bitlines.
|
||||
total_power = self.return_power(cell_power.dynamic + bitline_dynamic * self.column_size,
|
||||
cell_power.leakage * self.column_size * self.row_size)
|
||||
return total_power
|
||||
|
||||
def gen_wl_wire(self):
|
||||
if OPTS.netlist_only:
|
||||
width = 0
|
||||
else:
|
||||
width = self.width
|
||||
wl_wire = self.generate_rc_net(int(self.column_size), width, drc("minwidth_metal1"))
|
||||
wl_wire.wire_c = 2*spice["min_tx_gate_c"] + wl_wire.wire_c # 2 access tx gate per cell
|
||||
return wl_wire
|
||||
|
||||
def gen_bl_wire(self):
|
||||
if OPTS.netlist_only:
|
||||
height = 0
|
||||
else:
|
||||
height = self.height
|
||||
bl_pos = 0
|
||||
bl_wire = self.generate_rc_net(int(self.row_size-bl_pos), height, drc("minwidth_metal1"))
|
||||
bl_wire.wire_c =spice["min_tx_drain_c"] + bl_wire.wire_c # 1 access tx d/s per cell
|
||||
return bl_wire
|
||||
|
||||
def output_load(self, bl_pos=0):
|
||||
bl_wire = self.gen_bl_wire()
|
||||
return bl_wire.wire_c # sense amp only need to charge small portion of the bl
|
||||
# set as one segment for now
|
||||
|
||||
def input_load(self):
|
||||
wl_wire = self.gen_wl_wire()
|
||||
return wl_wire.return_input_cap()
|
||||
|
||||
def get_wordline_cin(self):
|
||||
"""Get the relative input capacitance from the wordline connections in all the bitcell"""
|
||||
#A single wordline is connected to all the bitcells in a single row meaning the capacitance depends on the # of columns
|
||||
bitcell_wl_cin = self.cell.get_wl_cin()
|
||||
total_cin = bitcell_wl_cin * self.column_size
|
||||
return total_cin
|
||||
@@ -19,8 +19,7 @@ class replica_column(design.design):
|
||||
def __init__(self, name, rows):
|
||||
design.design.__init__(self, name)
|
||||
|
||||
# One extra row for the dummy row
|
||||
self.row_size = rows + 1
|
||||
self.row_size = rows
|
||||
|
||||
self.create_netlist()
|
||||
if not OPTS.netlist_only:
|
||||
@@ -35,6 +34,9 @@ class replica_column(design.design):
|
||||
self.place_instances()
|
||||
self.add_layout_pins()
|
||||
|
||||
self.height = self.row_size*self.cell.height
|
||||
self.width = self.cell.width
|
||||
|
||||
self.add_boundary()
|
||||
self.DRC_LVS()
|
||||
|
||||
@@ -53,6 +55,8 @@ class replica_column(design.design):
|
||||
def add_modules(self):
|
||||
self.replica_cell = factory.create(module_type="replica_bitcell")
|
||||
self.add_mod(self.replica_cell)
|
||||
self.dummy_cell = factory.create(module_type="dummy_bitcell")
|
||||
self.add_mod(self.dummy_cell)
|
||||
# Used for pin names only
|
||||
self.cell = factory.create(module_type="bitcell")
|
||||
|
||||
@@ -60,37 +64,32 @@ class replica_column(design.design):
|
||||
self.cell_inst = {}
|
||||
for row in range(self.row_size):
|
||||
name="rbc_{0}".format(row)
|
||||
self.cell_inst[row]=self.add_inst(name=name,
|
||||
mod=self.replica_cell)
|
||||
if row>0 and row<self.row_size-2:
|
||||
self.cell_inst[row]=self.add_inst(name=name,
|
||||
mod=self.replica_cell)
|
||||
else:
|
||||
self.cell_inst[row]=self.add_inst(name=name,
|
||||
mod=self.dummy_cell)
|
||||
self.connect_inst(self.list_bitcell_pins(0, row))
|
||||
|
||||
def create_layout(self):
|
||||
def place_instances(self):
|
||||
|
||||
# We increase it by a well enclosure so the precharges don't overlap our wells
|
||||
self.height = self.row_size*self.cell.height
|
||||
self.width = self.cell.width
|
||||
|
||||
yoffset = 0.0
|
||||
yoffset = 0
|
||||
for row in range(self.row_size):
|
||||
name = "bit_r{0}_{1}".format(row,"rbl")
|
||||
|
||||
# This is opposite of a bitcell array since we will be 1 row off
|
||||
if not row % 2:
|
||||
tempy = yoffset + self.cell.height
|
||||
dir_key = "MX"
|
||||
else:
|
||||
tempy = yoffset
|
||||
dir_key = ""
|
||||
else:
|
||||
tempy = yoffset + self.cell.height
|
||||
dir_key = "MX"
|
||||
|
||||
self.cell_inst[row].place(offset=[0.0, tempy],
|
||||
mirror=dir_key)
|
||||
yoffset += self.cell.height
|
||||
|
||||
self.add_layout_pins()
|
||||
|
||||
self.add_boundary()
|
||||
|
||||
self.DRC_LVS()
|
||||
|
||||
|
||||
def add_layout_pins(self):
|
||||
@@ -99,7 +98,7 @@ class replica_column(design.design):
|
||||
row_list = self.cell.list_all_wl_names()
|
||||
column_list = self.cell.list_all_bitline_names()
|
||||
|
||||
col = "rbl"
|
||||
col = "0"
|
||||
for cell_column in column_list:
|
||||
bl_pin = self.cell_inst[0].get_pin(cell_column)
|
||||
self.add_layout_pin(text=cell_column+"_{0}".format(col),
|
||||
|
||||
Reference in New Issue
Block a user