luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Make wire test programmatic

This commit is contained in:
Matthew Guthaus 2019-12-17 22:36:38 +00:00
parent c025ce6356
commit 449b0a7c28
1 changed files with 23 additions and 98 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

119
compiler/tests/03_wire_test.py
View File

@ -23,106 +23,31 @@ class wire_test(openram_test):
import tech import tech
import design import design
min_space = 2 * (tech.drc["minwidth_poly"] + layer_stacks = [tech.poly_stack] + tech.beol_stacks
tech.drc["minwidth_m1"])
layer_stack = tech.poly_stack
old_position_list = [[0, 0],
[0, 3 * min_space],
[1 * min_space, 3 * min_space],
[4 * min_space, 3 * min_space],
[4 * min_space, 0],
[7 * min_space, 0],
[7 * min_space, 4 * min_space],
[-1 * min_space, 4 * min_space],
[-1 * min_space, 0]]
position_list = [[x-min_space, y-min_space] for x,y in old_position_list]
w = design.design("wire_test1")
wire.wire(w, layer_stack, position_list)
self.local_drc_check(w)
min_space = 2 * (tech.drc["minwidth_poly"] + for reverse in [False, True]:
tech.drc["minwidth_m1"]) for stack in layer_stacks:
layer_stack = tech.poly_stack if reverse:
old_position_list = [[0, 0], layer_stack = stack[::-1]
[0, 3 * min_space], else:
[1 * min_space, 3 * min_space], layer_stack = stack
[4 * min_space, 3 * min_space],
[4 * min_space, 0],
[7 * min_space, 0],
[7 * min_space, 4 * min_space],
[-1 * min_space, 4 * min_space],
[-1 * min_space, 0]]
position_list = [[x+min_space, y+min_space] for x,y in old_position_list]
w = design.design("wire_test2")
wire.wire(w, layer_stack, position_list)
self.local_drc_check(w)
min_space = 2 * (tech.drc["minwidth_m2"] + min_space = 2 * (tech.drc["minwidth_{}".format(layer_stack[0])] +
tech.drc["minwidth_m1"]) tech.drc["minwidth_{}".format(layer_stack[2])])
layer_stack = tech.m1_stack
position_list = [[0, 0],
[0, 3 * min_space],
[1 * min_space, 3 * min_space],
[4 * min_space, 3 * min_space],
[4 * min_space, 0],
[7 * min_space, 0],
[7 * min_space, 4 * min_space],
[-1 * min_space, 4 * min_space],
[-1 * min_space, 0]]
w = design.design("wire_test3")
wire.wire(w, layer_stack, position_list)
self.local_drc_check(w)
position_list = [[0, 0],
min_space = 2 * (tech.drc["minwidth_m2"] + [0, 3 * min_space],
tech.drc["minwidth_m1"]) [1 * min_space, 3 * min_space],
layer_stack = tech.m2_stack[::-1] [4 * min_space, 3 * min_space],
position_list = [[0, 0], [4 * min_space, 0],
[0, 3 * min_space], [7 * min_space, 0],
[1 * min_space, 3 * min_space], [7 * min_space, 4 * min_space],
[4 * min_space, 3 * min_space], [-1 * min_space, 4 * min_space],
[4 * min_space, 0], [-1 * min_space, 0]]
[7 * min_space, 0], position_list = [[x - min_space, y - min_space] for x, y in position_list]
[7 * min_space, 4 * min_space], w = design.design("wire_test_{}".format("_".join(layer_stack)))
[-1 * min_space, 4 * min_space], wire.wire(w, layer_stack, position_list)
[-1 * min_space, 0]] self.local_drc_check(w)
w = design.design("wire_test4")
wire.wire(w, layer_stack, position_list)
self.local_drc_check(w)
min_space = 2 * (tech.drc["minwidth_m2"] +
tech.drc["minwidth_m3"])
layer_stack = tech.m2_stack
position_list = [[0, 0],
[0, 3 * min_space],
[1 * min_space, 3 * min_space],
[4 * min_space, 3 * min_space],
[4 * min_space, 0],
[7 * min_space, 0],
[7 * min_space, 4 * min_space],
[-1 * min_space, 4 * min_space],
[-1 * min_space, 0]]
position_list.reverse()
w = design.design("wire_test5")
wire.wire(w, layer_stack, position_list)
self.local_drc_check(w)
min_space = 2 * (tech.drc["minwidth_m2"] +
tech.drc["minwidth_m3"])
layer_stack = tech.m2_stack[::-1]
position_list = [[0, 0],
[0, 3 * min_space],
[1 * min_space, 3 * min_space],
[4 * min_space, 3 * min_space],
[4 * min_space, 0],
[7 * min_space, 0],
[7 * min_space, 4 * min_space],
[-1 * min_space, 4 * min_space],
[-1 * min_space, 0]]
position_list.reverse()
w = design.design("wire_test6")
wire.wire(w, layer_stack, position_list)
self.local_drc_check(w)
globals.end_openram() globals.end_openram()