From 449b0a7c28d8b4be4c8b17e675214ebecfe66703 Mon Sep 17 00:00:00 2001 From: Matthew Guthaus Date: Tue, 17 Dec 2019 22:36:38 +0000 Subject: [PATCH] Make wire test programmatic --- compiler/tests/03_wire_test.py | 121 +++++++-------------------------- 1 file changed, 23 insertions(+), 98 deletions(-) diff --git a/compiler/tests/03_wire_test.py b/compiler/tests/03_wire_test.py index ae4f8499..bd4b9345 100755 --- a/compiler/tests/03_wire_test.py +++ b/compiler/tests/03_wire_test.py @@ -22,107 +22,32 @@ class wire_test(openram_test): import wire import tech import design - - min_space = 2 * (tech.drc["minwidth_poly"] + - tech.drc["minwidth_m1"]) - layer_stack = tech.poly_stack - old_position_list = [[0, 0], - [0, 3 * min_space], - [1 * min_space, 3 * min_space], - [4 * min_space, 3 * min_space], - [4 * min_space, 0], - [7 * min_space, 0], - [7 * min_space, 4 * min_space], - [-1 * min_space, 4 * min_space], - [-1 * min_space, 0]] - position_list = [[x-min_space, y-min_space] for x,y in old_position_list] - w = design.design("wire_test1") - wire.wire(w, layer_stack, position_list) - self.local_drc_check(w) - min_space = 2 * (tech.drc["minwidth_poly"] + - tech.drc["minwidth_m1"]) - layer_stack = tech.poly_stack - old_position_list = [[0, 0], - [0, 3 * min_space], - [1 * min_space, 3 * min_space], - [4 * min_space, 3 * min_space], - [4 * min_space, 0], - [7 * min_space, 0], - [7 * min_space, 4 * min_space], - [-1 * min_space, 4 * min_space], - [-1 * min_space, 0]] - position_list = [[x+min_space, y+min_space] for x,y in old_position_list] - w = design.design("wire_test2") - wire.wire(w, layer_stack, position_list) - self.local_drc_check(w) + layer_stacks = [tech.poly_stack] + tech.beol_stacks - min_space = 2 * (tech.drc["minwidth_m2"] + - tech.drc["minwidth_m1"]) - layer_stack = tech.m1_stack - position_list = [[0, 0], - [0, 3 * min_space], - [1 * min_space, 3 * min_space], - [4 * min_space, 3 * min_space], - [4 * min_space, 0], - [7 * min_space, 0], - [7 * min_space, 4 * min_space], - [-1 * min_space, 4 * min_space], - [-1 * min_space, 0]] - w = design.design("wire_test3") - wire.wire(w, layer_stack, position_list) - self.local_drc_check(w) + for reverse in [False, True]: + for stack in layer_stacks: + if reverse: + layer_stack = stack[::-1] + else: + layer_stack = stack + + min_space = 2 * (tech.drc["minwidth_{}".format(layer_stack[0])] + + tech.drc["minwidth_{}".format(layer_stack[2])]) - - min_space = 2 * (tech.drc["minwidth_m2"] + - tech.drc["minwidth_m1"]) - layer_stack = tech.m2_stack[::-1] - position_list = [[0, 0], - [0, 3 * min_space], - [1 * min_space, 3 * min_space], - [4 * min_space, 3 * min_space], - [4 * min_space, 0], - [7 * min_space, 0], - [7 * min_space, 4 * min_space], - [-1 * min_space, 4 * min_space], - [-1 * min_space, 0]] - w = design.design("wire_test4") - wire.wire(w, layer_stack, position_list) - self.local_drc_check(w) - - min_space = 2 * (tech.drc["minwidth_m2"] + - tech.drc["minwidth_m3"]) - layer_stack = tech.m2_stack - position_list = [[0, 0], - [0, 3 * min_space], - [1 * min_space, 3 * min_space], - [4 * min_space, 3 * min_space], - [4 * min_space, 0], - [7 * min_space, 0], - [7 * min_space, 4 * min_space], - [-1 * min_space, 4 * min_space], - [-1 * min_space, 0]] - position_list.reverse() - w = design.design("wire_test5") - wire.wire(w, layer_stack, position_list) - self.local_drc_check(w) - - min_space = 2 * (tech.drc["minwidth_m2"] + - tech.drc["minwidth_m3"]) - layer_stack = tech.m2_stack[::-1] - position_list = [[0, 0], - [0, 3 * min_space], - [1 * min_space, 3 * min_space], - [4 * min_space, 3 * min_space], - [4 * min_space, 0], - [7 * min_space, 0], - [7 * min_space, 4 * min_space], - [-1 * min_space, 4 * min_space], - [-1 * min_space, 0]] - position_list.reverse() - w = design.design("wire_test6") - wire.wire(w, layer_stack, position_list) - self.local_drc_check(w) + position_list = [[0, 0], + [0, 3 * min_space], + [1 * min_space, 3 * min_space], + [4 * min_space, 3 * min_space], + [4 * min_space, 0], + [7 * min_space, 0], + [7 * min_space, 4 * min_space], + [-1 * min_space, 4 * min_space], + [-1 * min_space, 0]] + position_list = [[x - min_space, y - min_space] for x, y in position_list] + w = design.design("wire_test_{}".format("_".join(layer_stack))) + wire.wire(w, layer_stack, position_list) + self.local_drc_check(w) globals.end_openram()