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Fix missing via for global wordlines.

This commit is contained in:
mrg 2021-04-21 11:33:18 -07:00
parent f45efe3db6
commit 419836411c
1 changed files with 11 additions and 8 deletions
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19
compiler/modules/local_bitcell_array.py
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@ -217,17 +217,20 @@ class local_bitcell_array(bitcell_base_array.bitcell_base_array):
y_offset += global_wl_pitch_factor * global_wl_pitch y_offset += global_wl_pitch_factor * global_wl_pitch
mid = vector(in_pin.cx(), y_offset) mid = vector(in_pin.cx(), y_offset)
# A short jog to the global line
self.add_via_stack_center(from_layer=in_pin.layer,
to_layer=local_wl_layer,
offset=in_pin.center(),
min_area=True)
self.add_path(local_wl_layer, [in_pin.center(), mid])
self.add_via_stack_center(from_layer=local_wl_layer,
to_layer=global_wl_layer,
offset=mid,
min_area=True)
# Add the global WL pin
self.add_layout_pin_rect_center(text=wl_name, self.add_layout_pin_rect_center(text=wl_name,
layer=global_wl_layer, layer=global_wl_layer,
offset=mid) offset=mid)
self.add_path(local_wl_layer, [in_pin.center(), mid])
self.add_via_stack_center(from_layer=in_pin.layer,
to_layer=local_wl_layer,
offset=mid,
min_area=True)
# Route the buffers # Route the buffers
for port in self.all_ports: for port in self.all_ports:
driver_outputs = self.driver_wordline_outputs[port] driver_outputs = self.driver_wordline_outputs[port]