diff --git a/compiler/modules/local_bitcell_array.py b/compiler/modules/local_bitcell_array.py
index 68552d57..30da5bf1 100644
--- a/compiler/modules/local_bitcell_array.py
+++ b/compiler/modules/local_bitcell_array.py
@@ -217,17 +217,20 @@ class local_bitcell_array(bitcell_base_array.bitcell_base_array):
                     y_offset += global_wl_pitch_factor * global_wl_pitch
                 mid = vector(in_pin.cx(), y_offset)
 
+                # A short jog to the global line
+                self.add_via_stack_center(from_layer=in_pin.layer,
+                                          to_layer=local_wl_layer,
+                                          offset=in_pin.center(),
+                                          min_area=True)
+                self.add_path(local_wl_layer, [in_pin.center(), mid])
+                self.add_via_stack_center(from_layer=local_wl_layer,
+                                          to_layer=global_wl_layer,
+                                          offset=mid,
+                                          min_area=True)
+                # Add the global WL pin
                 self.add_layout_pin_rect_center(text=wl_name,
                                                 layer=global_wl_layer,
                                                 offset=mid)
-
-                self.add_path(local_wl_layer, [in_pin.center(), mid])
-
-                self.add_via_stack_center(from_layer=in_pin.layer,
-                                          to_layer=local_wl_layer,
-                                          offset=mid,
-                                          min_area=True)
-
         # Route the buffers
         for port in self.all_ports:
             driver_outputs = self.driver_wordline_outputs[port]