diff --git a/compiler/bitcells/bitcell.py b/compiler/bitcells/bitcell.py
index 4ed2d053..e91d8c2f 100644
--- a/compiler/bitcells/bitcell.py
+++ b/compiler/bitcells/bitcell.py
@@ -10,7 +10,7 @@ import utils
 from tech import GDS, layer
 from tech import cell_properties as props
 import bitcell_base
-
+from globals import OPTS
 
 class bitcell(bitcell_base.bitcell_base):
     """
@@ -50,6 +50,8 @@ class bitcell(bitcell_base.bitcell_base):
         self.pin_map = bitcell.pin_map
         self.add_pin_types(self.type_list)
         self.nets_match = self.do_nets_exist(self.storage_nets)
+
+        debug.check(OPTS.tech_name != "sky130", "sky130 does not yet support single port cells")
               
     def get_all_wl_names(self):
         """ Creates a list of all wordline pin names """