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Fixed key error with analytical delay of write ports.

This commit is contained in:
Hunter Nichols 2019-06-28 13:49:04 -07:00
parent ce7e320505
commit 3f5b60856a
1 changed files with 1 additions and 0 deletions
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compiler/sram/sram_base.py
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@ -529,6 +529,7 @@ class sram_base(design, verilog, lef):
elif port in self.readwrite_ports: elif port in self.readwrite_ports:
control_logic = self.control_logic_rw control_logic = self.control_logic_rw
else: else:
delays[port] = self.return_delay(0,0) #Write ports do not have a lib defined delay, marked as 0
continue continue
clk_to_wlen_delays = control_logic.analytical_delay(corner, slew, load) clk_to_wlen_delays = control_logic.analytical_delay(corner, slew, load)
wlen_to_dout_delays = self.bank.analytical_delay(corner,slew,load,port) #port should probably be specified... wlen_to_dout_delays = self.bank.analytical_delay(corner,slew,load,port) #port should probably be specified...